For every POD the following information is given:
•Ordering code. If there are different speed versions of a POD the ordering code is modified by appending the speed in MHz
•information on available speed versions and required Emulator access time
•POD size and position of PIN1 on the target adapter relative to bottom left corner.
The memory range specifies the range of addresses that a POD can address. If this specification is omitted the default 1MB is assumed.
Note: The
Beside that,
Final Target Application Test
After the application is being more or less debugged and final application test is performed, it is recommended to remove all breakpoints and to close all debug windows (memory, SFR, watch...) to eliminate any possible influence of the emulator on the CPU execution. There were cases where the target application has been behaving differently with the target CPU inserted or the POD connected. If the debugger is configured to update some debug windows in
There are cases when internal peripheral device requires read access of the particular register during the device configuration. The user has had SFR window opened and the necessary read access was actually performed by the debugger and not by the application as it would be correct. Therefore, the application was working fine with the emulator, but a standalone application didn't work correctly, as the peripheral device was not configured properly.
For Better Understanding of the Hardware Reference: PIN 1 locations
There are several references to pin 1 in the manual and many jumper settings, CPU and pinout orientations rely on the correct location of pin 1. If sometimes the location of pin 1 is not clear, check the markings on the POD. If there are no markings, check the PCB board of the POD. Pin 1 is always marked on the PCB with a square pin (the other pins are round). The pin 1 location is also visible on the board in the hardware reference, if not any other way it can be identified by searching for the square pin.
iSYSTEM, March 2004 | 3/12 |