Silicon Laboratories SI5351A/B/C Synthesis Stages, Output Stage, External Clock Input Clkin

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Si5351A/B/C

3.1.2. External Clock Input (CLKIN)

The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs. CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to 30 MHz.

3.1.3. Voltage Control Input (VC)

The VCXO architecture of the Si5350B eliminates the need for an external pullable crystal. Only a standard, low- cost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.

The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and reliable startup and operation. Refer to Table 3 on page 5 for VCXO specification details.

A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same reference. An example is illustrated in Figure 9 on page 15.

3.2. Synthesis Stages

The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply the lower frequency input references to a high-frequency intermediate clock. The second stage uses high- resolution MultiSynth fractional dividers to generate frequencies in the range of 1 MHz to 100 MHz. It is also possible to generate two unique frequencies up to 160 MHz on two or more of the outputs.

A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input. This allows each of the PLLs to lock to a different source for generating independent free-running and synchronous clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.

Since the VCXO already generates a high-frequency intermediate clock, it is fed directly into the second stage of synthesis. The MultiSynth high-resolution dividers synthesize the VCXO center frequency to any frequency in the range of ~391 kHz to 160 MHz. The center frequency is then controlled (or pulled) by the VC input. An interesting feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This creates a VCXO with multiple output frequencies controlled from one VC input as shown in Figure 5.

Frequencies down to 8 kHz can be generated by applying the R divider at the output of the Multisynth (see Figure 5 below).

XA

Fixed Frequency XB Crystal (non-pullable)

Control VC Voltage

OSC

VCXO

Multi

Synth

0

Multi

Synth

1

Multi

Synth

2

The clock frequency

R0 CLK0 generated from CLK0 is controlled by the VC input

R1 CLK1

Additional MultiSynths

R2 CLK2 can be “linked” to the VCXO to generate

additional clock

frequencies

Figure 5. Using the Si5351 as a Multi-Output VCXO

3.3. Output Stage

An additional level of division (R) is available at the output stage for generating clocks as low as 8 kHz. All output drivers generate CMOS level outputs with separate output voltage supply pins (VDDOx) allowing a different voltage signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks.

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Contents Features Functional Block DiagramApplications DescriptionSi5351A/B/C Table of Contents Electrical Specifications DC CharacteristicsParameter Symbol Test Condition Min Typ Max Unit Recommended Operating ConditionsAC Characteristics Input Clock CharacteristicsVcxo Specifications Si5351B only Parameter Symbol Test Condition Min Typ Max UnitsOutput Clock Characteristics Parameter Symbol Min Typ Max UnitCrystal Requirements1,2 I2C Specifications SCL,SDA1 Thermal CharacteristicsParameter Symbol Test Condition Package Value Unit Parameter Symbol Test Condition Value Unit Absolute Maximum Ratings1Detailed Block Diagrams Block Diagrams of 3-Output and 8-Output Si5351A DevicesBlock Diagrams of Si5351B and Si5351C 8-Output Devices Functional Description Input StageCrystal Inputs XA, XB Synthesis Stages Output StageExternal Clock Input Clkin Voltage Control Input VCControl Pins OEB, Ssen Output Enable OEBSpread Spectrum Enable SSEN-Si5351A and Si5351B only Spread SpectrumI2C and Control Signals I2C InterfaceI2C Write Operation Configuring the Si5351 Writing a Custom Configuration to RAMPower-Up I2C Programming Procedure Si5351 Application Examples Replacing Crystals and Crystal OscillatorsReplacing Crystals, Crystal Oscillators, and VCXOs Replacing Crystals, Crystal Oscillators, and PLLsSi5351B Si5351CReplacing a Crystal with a Clock Hcsl Compatible OutputsDesign Considerations Trace Characteristics Register Map Summary RegisterCLK0PHOFF70 Register Descriptions Clkin Loss Of Signal Sticky Bit Si5351C Only Register 1. Interrupt Status StickySystem Calibration Status Sticky Bit Pllb Loss Of Lock Status Sticky BitClkin Loss Of Signal Mask Si5351C Only Register 2. Interrupt Status MaskSystem Initialization Status Mask Pllb Loss Of Lock Status MaskRegister 3. Output Enable Control Output Disable for CLKxRegister 9. OEB Pin Enable Control OEB pin enable control of CLKxRegister 15. PLL Input Source PllbsrcClock 0 Power Down MultiSynth 0 Integer ModeRegister 16. CLK0 Control Bit Name FunctionClock 1 Power Down MultiSynth 1 Integer ModeRegister 17. CLK1 Control MultiSynth Source Select for CLK1Clock 2 Power Down MultiSynth 2 Integer ModeRegister 18. CLK2 Control MultiSynth Source Select for CLK2Clock 3 Power Down MultiSynth 3 Integer ModeRegister 19. CLK3 Control MultiSynth Source Select for CLK3Clock 4 Power Down MultiSynth 4 Integer ModeRegister 20. CLK4 Control MultiSynth Source Select for CLK4Clock 5 Power Down MultiSynth 5 Integer ModeRegister 21. CLK5 Control MultiSynth Source Select for CLK5Clock 7 Power Down FBA MultiSynth Integer ModeRegister 22. CLK6 Control MultiSynth Source Select for CLK6FBB MultiSynth Integer Mode Register 23. CLK7 ControlMultiSynth Source Select for CLK7 Output Clock 7 InvertRegister 24. CLK3-0 Disable State Bit Name Function CLKxDISSTATE Clock x Disable StateRegister 25. CLK7-4 Disable State Clock x Disable StateMS0P3158 Type Reset value Register 42. Multisynth0 Parameters BitMS0P370 Register 44. Multisynth0 Parameters Bit R0 Output DividerRegister 45. Multisynth0 Parameters Bit Register 46. Multisynth0 Parameters Bit MS0P170MS0P31916 MS0P21916 MS0P2158Register 49. Multisynth0 Parameters Bit MS0P270MS1P3158 MS1P370Register 52. Multisynth1 Parameters Bit R1 Output DividerRegister 53. Multisynth1 Parameters Bit Register 54. Multisynth1 Parameters Bit Name MS1P170 MS1P31916 MS1P21916Register 57. Multisynth1 Parameters Bit MS1P270Register 60. Multisynth2 Parameters Bit R2 Output DividerMultisynth2 Parameter Register 61. Multisynth2 Parameters BitRegister 62. Multisynth2 Parameters Bit Name MS2P170 MS2P31916 MS2P21916Register 65. Multisynth2 Parameters Bit MS2P270MS3P3158 MS3P370Register 68. Multisynth3 Parameters Bit R3 Output DividerRegister 69. Multisynth3 Parameters Bit Register 70. Multisynth3 Parameters Bit Name MS3P170 MS3P31916 MS3P21916Register 73. Multisynth3 Parameters Bit MS3P270MS4P3158 MS4P370Register 76. Multisynth4 Parameters Bit R4 Output DividerRegister 77. Multisynth4 Parameters Bit Register 78. Multisynth4 Parameters Bit Name MS4P170 MS4P31916 MS4P21916Register 81. Multisynth4 Parameters Bit MS4P270MS5P3158 MS5P370Register 84. Multisynth5 Parameters Bit R5 Output DividerRegister 85. Multisynth5 Parameters Bit Register 86. Multisynth5 Parameters Bit Name MS5P170 MS5P31916 MS5P21916Register 89. Multisynth5 Parameters Bit MS5P270MS6P170 MS7P170Register 92. Clock 6 and 7 Output Divider Bit R7 Output DividerR6 Output Divider Register 165. CLK0 Initial Phase Offset Clock 0 Initial Phase OffsetRegister 166. CLK1 Initial Phase Offset Clock 1 Initial Phase OffsetRegister 168. CLK3 Initial Phase Offset Clock 3 Initial Phase OffsetRegister 169. CLK4 Initial Phase Offset Clock 4 Initial Phase OffsetRegister 177. PLL Reset PLLBResetPLLAReset Register 183. Crystal Internal Load CapacitanceSi5351A Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351A Pin DescriptionsPin Name Pin Number Pin Type Function 20-QFN 10. Si5351B Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351B Pin Descriptions11. Si5351C Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351C Pin Descriptions12. Si5351A Pin Descriptions 10-Pin Msop Si5351A 10-MSOP Pin DescriptionsPin NumberOrdering Information Si5351X Device Part NumbersQsop Package Dimensions Dimension Min Nom MaxPackage Outline 24-Pin Qsop Package Dimensions Dimension Min NomPackage Outline 20-Pin QFN Package Outline 10-Pin Msop DddRevision 0.1 to Revision Revision 0.9 to RevisionSi5351A/B/C Contact Information

SI5351A/B/C specifications

Silicon Laboratories SI5351A/B/C is a versatile, low-power clock generator and frequency synthesizer that has gained widespread popularity in various applications, including telecommunications, consumer electronics, and industrial control systems. These devices are primarily designed to provide precise clock frequency generation with low phase noise and jitter, making them ideal for high-performance applications.

One of the standout features of the SI5351 is its ability to generate multiple output frequencies simultaneously. Capable of producing up to three independent programmable outputs, the SI5351A/B/C can generate frequencies ranging from 8 kHz to 160 MHz. With its integrated phase-locked loop (PLL) technology, it achieves excellent frequency stability and accuracy, simplifying the design of frequency-dependent systems.

The device operates under a supply voltage range of 1.8V to 3.6V, allowing it to be used in battery-powered applications without excessive power consumption. The SI5351’s low current draw, typically as low as 25 mA, is especially beneficial in portable devices, extending battery life and enhancing overall efficiency. Furthermore, it features a programmable output driver, which can be set to various drive strengths, ensuring compatibility with a wide array of load requirements.

Configuration and control of the SI5351 are user-friendly, implemented via an I2C interface. This allows for straightforward integration into microcontroller-based designs. Moreover, the device includes an on-chip memory that stores settings, which streamlines the reconfiguration process when power cycling, minimizing setup time for developers.

Another significant advantage of the SI5351A/B/C is its output jitter performance, which is typically below 1 ps, resulting in clean output signals essential for high-speed data communications and precise timing applications. The SI5351’s integration of multiple synthesizer stages contributes to its impressive phase noise characteristics, making it suitable for demanding RF applications.

Additionally, the SI5351 devices offer programmable frequency stepping, allowing users to define custom frequency increments, which is particularly useful in applications requiring precise tuning or modulation. This flexibility, combined with its compact size and simple interface, makes the SI5351A/B/C an ideal choice for engineers seeking a reliable, cost-effective solution for generating clock signals in a myriad of electronic systems.

In summary, Silicon Laboratories SI5351A/B/C provides a robust, low-power solution for high-precision clock generation, characterized by its programmable outputs, low jitter, easy configurability, and broad frequency range, making it an excellent choice for both commercial and industrial applications across various sectors.
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