Silicon Laboratories SI5351A/B/C Replacing a Crystal with a Clock, Hcsl Compatible Outputs

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Si5351A/B/C

5.6. Replacing a Crystal with a Clock

The Si5351 can be driven with a clock signal through the XA input pin.

VIN = 1 VPP

 

 

 

 

25/27 MHz

 

 

XA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.1 µF

XB

Note: Float the XB input while driving the XA input with a clock

OSC

PLLA

PLLB

Multi

Synth

0

Multi

Synth

1

Multi

Synth

N

Figure 16. Si5351 Driven by a Clock Signal

5.7. HCSL Compatible Outputs

The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).

The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair must also be inverted to generate a differential pair. See register setting CLKx_INV.

OSC

PLLA

PLLB

Multi

Synth

0

Multi

Synth

1

Multi

Synth

N

ZO = 70 Ω

R1

0 Ω

511 Ω

240 Ω R2

ZO = 70 Ω

R1

0 Ω

511 Ω

240 Ω R2

Note: The complementary -180 degree out of phase output clock is generated using the INV function

HCSL CLKIN

Figure 17. Si5350C Output is HCSL Compatible

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Preliminary Rev. 0.95

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Contents Features Functional Block DiagramApplications DescriptionSi5351A/B/C Table of Contents Electrical Specifications DC CharacteristicsParameter Symbol Test Condition Min Typ Max Unit Recommended Operating ConditionsAC Characteristics Input Clock CharacteristicsVcxo Specifications Si5351B only Parameter Symbol Test Condition Min Typ Max UnitsCrystal Requirements1,2 Output Clock CharacteristicsParameter Symbol Min Typ Max Unit Parameter Symbol Test Condition Package Value Unit I2C Specifications SCL,SDA1Thermal Characteristics Parameter Symbol Test Condition Value Unit Absolute Maximum Ratings1Detailed Block Diagrams Block Diagrams of 3-Output and 8-Output Si5351A DevicesBlock Diagrams of Si5351B and Si5351C 8-Output Devices Crystal Inputs XA, XB Functional DescriptionInput Stage Synthesis Stages Output StageExternal Clock Input Clkin Voltage Control Input VCControl Pins OEB, Ssen Output Enable OEBSpread Spectrum Enable SSEN-Si5351A and Si5351B only Spread SpectrumI2C and Control Signals I2C InterfaceI2C Write Operation Power-Up Configuring the Si5351Writing a Custom Configuration to RAM I2C Programming Procedure Si5351 Application Examples Replacing Crystals and Crystal OscillatorsReplacing Crystals, Crystal Oscillators, and VCXOs Replacing Crystals, Crystal Oscillators, and PLLsSi5351B Si5351CReplacing a Crystal with a Clock Hcsl Compatible OutputsDesign Considerations Trace Characteristics Register Map Summary RegisterCLK0PHOFF70 Register Descriptions Clkin Loss Of Signal Sticky Bit Si5351C Only Register 1. Interrupt Status StickySystem Calibration Status Sticky Bit Pllb Loss Of Lock Status Sticky BitClkin Loss Of Signal Mask Si5351C Only Register 2. Interrupt Status MaskSystem Initialization Status Mask Pllb Loss Of Lock Status MaskRegister 3. Output Enable Control Output Disable for CLKxRegister 9. OEB Pin Enable Control OEB pin enable control of CLKxRegister 15. PLL Input Source PllbsrcClock 0 Power Down MultiSynth 0 Integer ModeRegister 16. CLK0 Control Bit Name FunctionClock 1 Power Down MultiSynth 1 Integer ModeRegister 17. CLK1 Control MultiSynth Source Select for CLK1Clock 2 Power Down MultiSynth 2 Integer ModeRegister 18. CLK2 Control MultiSynth Source Select for CLK2Clock 3 Power Down MultiSynth 3 Integer ModeRegister 19. CLK3 Control MultiSynth Source Select for CLK3Clock 4 Power Down MultiSynth 4 Integer ModeRegister 20. CLK4 Control MultiSynth Source Select for CLK4Clock 5 Power Down MultiSynth 5 Integer ModeRegister 21. CLK5 Control MultiSynth Source Select for CLK5Clock 7 Power Down FBA MultiSynth Integer ModeRegister 22. CLK6 Control MultiSynth Source Select for CLK6FBB MultiSynth Integer Mode Register 23. CLK7 ControlMultiSynth Source Select for CLK7 Output Clock 7 InvertRegister 24. CLK3-0 Disable State Bit Name Function CLKxDISSTATE Clock x Disable StateRegister 25. CLK7-4 Disable State Clock x Disable StateMS0P370 MS0P3158 Type Reset valueRegister 42. Multisynth0 Parameters Bit Register 45. Multisynth0 Parameters Bit Register 44. Multisynth0 Parameters BitR0 Output Divider Register 46. Multisynth0 Parameters Bit MS0P170MS0P31916 MS0P21916 MS0P2158Register 49. Multisynth0 Parameters Bit MS0P270MS1P3158 MS1P370Register 53. Multisynth1 Parameters Bit Register 52. Multisynth1 Parameters BitR1 Output Divider Register 54. Multisynth1 Parameters Bit Name MS1P170 MS1P31916 MS1P21916Register 57. Multisynth1 Parameters Bit MS1P270Register 60. Multisynth2 Parameters Bit R2 Output DividerMultisynth2 Parameter Register 61. Multisynth2 Parameters BitRegister 62. Multisynth2 Parameters Bit Name MS2P170 MS2P31916 MS2P21916Register 65. Multisynth2 Parameters Bit MS2P270MS3P3158 MS3P370Register 69. Multisynth3 Parameters Bit Register 68. Multisynth3 Parameters BitR3 Output Divider Register 70. Multisynth3 Parameters Bit Name MS3P170 MS3P31916 MS3P21916Register 73. Multisynth3 Parameters Bit MS3P270MS4P3158 MS4P370Register 77. Multisynth4 Parameters Bit Register 76. Multisynth4 Parameters BitR4 Output Divider Register 78. Multisynth4 Parameters Bit Name MS4P170 MS4P31916 MS4P21916Register 81. Multisynth4 Parameters Bit MS4P270MS5P3158 MS5P370Register 85. Multisynth5 Parameters Bit Register 84. Multisynth5 Parameters BitR5 Output Divider Register 86. Multisynth5 Parameters Bit Name MS5P170 MS5P31916 MS5P21916Register 89. Multisynth5 Parameters Bit MS5P270MS6P170 MS7P170R6 Output Divider Register 92. Clock 6 and 7 Output Divider BitR7 Output Divider Register 165. CLK0 Initial Phase Offset Clock 0 Initial Phase OffsetRegister 166. CLK1 Initial Phase Offset Clock 1 Initial Phase OffsetRegister 168. CLK3 Initial Phase Offset Clock 3 Initial Phase OffsetRegister 169. CLK4 Initial Phase Offset Clock 4 Initial Phase OffsetRegister 177. PLL Reset PLLBResetPLLAReset Register 183. Crystal Internal Load CapacitancePin Name Pin Number Pin Type Function 20-QFN Si5351A Pin Descriptions 20-Pin QFN, 24-Pin QsopSi5351A Pin Descriptions 10. Si5351B Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351B Pin Descriptions11. Si5351C Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351C Pin Descriptions12. Si5351A Pin Descriptions 10-Pin Msop Si5351A 10-MSOP Pin DescriptionsPin NumberOrdering Information Si5351X Device Part NumbersPackage Outline 24-Pin Qsop Qsop Package DimensionsDimension Min Nom Max Package Outline 20-Pin QFN Package DimensionsDimension Min Nom Package Outline 10-Pin Msop DddRevision 0.1 to Revision Revision 0.9 to RevisionSi5351A/B/C Contact Information

SI5351A/B/C specifications

Silicon Laboratories SI5351A/B/C is a versatile, low-power clock generator and frequency synthesizer that has gained widespread popularity in various applications, including telecommunications, consumer electronics, and industrial control systems. These devices are primarily designed to provide precise clock frequency generation with low phase noise and jitter, making them ideal for high-performance applications.

One of the standout features of the SI5351 is its ability to generate multiple output frequencies simultaneously. Capable of producing up to three independent programmable outputs, the SI5351A/B/C can generate frequencies ranging from 8 kHz to 160 MHz. With its integrated phase-locked loop (PLL) technology, it achieves excellent frequency stability and accuracy, simplifying the design of frequency-dependent systems.

The device operates under a supply voltage range of 1.8V to 3.6V, allowing it to be used in battery-powered applications without excessive power consumption. The SI5351’s low current draw, typically as low as 25 mA, is especially beneficial in portable devices, extending battery life and enhancing overall efficiency. Furthermore, it features a programmable output driver, which can be set to various drive strengths, ensuring compatibility with a wide array of load requirements.

Configuration and control of the SI5351 are user-friendly, implemented via an I2C interface. This allows for straightforward integration into microcontroller-based designs. Moreover, the device includes an on-chip memory that stores settings, which streamlines the reconfiguration process when power cycling, minimizing setup time for developers.

Another significant advantage of the SI5351A/B/C is its output jitter performance, which is typically below 1 ps, resulting in clean output signals essential for high-speed data communications and precise timing applications. The SI5351’s integration of multiple synthesizer stages contributes to its impressive phase noise characteristics, making it suitable for demanding RF applications.

Additionally, the SI5351 devices offer programmable frequency stepping, allowing users to define custom frequency increments, which is particularly useful in applications requiring precise tuning or modulation. This flexibility, combined with its compact size and simple interface, makes the SI5351A/B/C an ideal choice for engineers seeking a reliable, cost-effective solution for generating clock signals in a myriad of electronic systems.

In summary, Silicon Laboratories SI5351A/B/C provides a robust, low-power solution for high-precision clock generation, characterized by its programmable outputs, low jitter, easy configurability, and broad frequency range, making it an excellent choice for both commercial and industrial applications across various sectors.
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