Silicon Laboratories SI5351A/B/C Package Outline 24-Pin Qsop, Qsop Package Dimensions

Page 67

Si5351A/B/C

14. Package Outline (24-Pin QSOP)

Table 14. 24-QSOP Package Dimensions

Dimension

Min

Nom

Max

 

 

 

 

A

—

—

1.75

 

 

 

 

A1

0.10

—

0.25

 

 

 

 

b

0.19

—

0.30

 

 

 

 

c

0.15

—

0.25

 

 

 

 

D

8.55

8.65

8.75

 

 

 

 

E

 

6.00 BSC

 

 

 

 

 

E1

3.81

3.90

3.99

 

 

 

 

e

 

0.635 BSC

 

 

 

 

 

L

0.40

—

1.27

 

 

 

 

L2

 

0.25 BSC

 

 

 

 

 

q

0

—

8

 

 

 

 

aaa

 

0.10

 

 

 

 

 

bbb

 

0.17

 

 

 

 

 

ccc

 

0.10

 

 

 

 

 

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Preliminary Rev. 0.95

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Contents Description FeaturesFunctional Block Diagram ApplicationsSi5351A/B/C Table of Contents Recommended Operating Conditions Electrical SpecificationsDC Characteristics Parameter Symbol Test Condition Min Typ Max UnitParameter Symbol Test Condition Min Typ Max Units AC CharacteristicsInput Clock Characteristics Vcxo Specifications Si5351B onlyParameter Symbol Min Typ Max Unit Output Clock CharacteristicsCrystal Requirements1,2 Thermal Characteristics I2C Specifications SCL,SDA1Parameter Symbol Test Condition Package Value Unit Absolute Maximum Ratings1 Parameter Symbol Test Condition Value UnitBlock Diagrams of 3-Output and 8-Output Si5351A Devices Detailed Block DiagramsBlock Diagrams of Si5351B and Si5351C 8-Output Devices Input Stage Functional DescriptionCrystal Inputs XA, XB Voltage Control Input VC Synthesis StagesOutput Stage External Clock Input ClkinSpread Spectrum Control Pins OEB, SsenOutput Enable OEB Spread Spectrum Enable SSEN-Si5351A and Si5351B onlyI2C Interface I2C and Control SignalsI2C Write Operation Writing a Custom Configuration to RAM Configuring the Si5351Power-Up I2C Programming Procedure Replacing Crystals and Crystal Oscillators Si5351 Application ExamplesSi5351C Replacing Crystals, Crystal Oscillators, and VCXOsReplacing Crystals, Crystal Oscillators, and PLLs Si5351BHcsl Compatible Outputs Replacing a Crystal with a ClockDesign Considerations Trace Characteristics Register Register Map SummaryCLK0PHOFF70 Register Descriptions Pllb Loss Of Lock Status Sticky Bit Clkin Loss Of Signal Sticky Bit Si5351C OnlyRegister 1. Interrupt Status Sticky System Calibration Status Sticky BitPllb Loss Of Lock Status Mask Clkin Loss Of Signal Mask Si5351C OnlyRegister 2. Interrupt Status Mask System Initialization Status MaskOEB pin enable control of CLKx Register 3. Output Enable ControlOutput Disable for CLKx Register 9. OEB Pin Enable ControlPllbsrc Register 15. PLL Input SourceBit Name Function Clock 0 Power DownMultiSynth 0 Integer Mode Register 16. CLK0 ControlMultiSynth Source Select for CLK1 Clock 1 Power DownMultiSynth 1 Integer Mode Register 17. CLK1 ControlMultiSynth Source Select for CLK2 Clock 2 Power DownMultiSynth 2 Integer Mode Register 18. CLK2 ControlMultiSynth Source Select for CLK3 Clock 3 Power DownMultiSynth 3 Integer Mode Register 19. CLK3 ControlMultiSynth Source Select for CLK4 Clock 4 Power DownMultiSynth 4 Integer Mode Register 20. CLK4 ControlMultiSynth Source Select for CLK5 Clock 5 Power DownMultiSynth 5 Integer Mode Register 21. CLK5 ControlMultiSynth Source Select for CLK6 Clock 7 Power DownFBA MultiSynth Integer Mode Register 22. CLK6 ControlOutput Clock 7 Invert FBB MultiSynth Integer ModeRegister 23. CLK7 Control MultiSynth Source Select for CLK7Clock x Disable State Register 24. CLK3-0 Disable StateBit Name Function CLKxDISSTATE Clock x Disable State Register 25. CLK7-4 Disable StateRegister 42. Multisynth0 Parameters Bit MS0P3158 Type Reset valueMS0P370 R0 Output Divider Register 44. Multisynth0 Parameters BitRegister 45. Multisynth0 Parameters Bit MS0P2158 Register 46. Multisynth0 Parameters BitMS0P170 MS0P31916 MS0P21916MS1P370 Register 49. Multisynth0 Parameters BitMS0P270 MS1P3158R1 Output Divider Register 52. Multisynth1 Parameters BitRegister 53. Multisynth1 Parameters Bit MS1P31916 MS1P21916 Register 54. Multisynth1 Parameters Bit Name MS1P170MS1P270 Register 57. Multisynth1 Parameters BitRegister 61. Multisynth2 Parameters Bit Register 60. Multisynth2 Parameters BitR2 Output Divider Multisynth2 ParameterMS2P31916 MS2P21916 Register 62. Multisynth2 Parameters Bit Name MS2P170MS3P370 Register 65. Multisynth2 Parameters BitMS2P270 MS3P3158R3 Output Divider Register 68. Multisynth3 Parameters BitRegister 69. Multisynth3 Parameters Bit MS3P31916 MS3P21916 Register 70. Multisynth3 Parameters Bit Name MS3P170MS4P370 Register 73. Multisynth3 Parameters BitMS3P270 MS4P3158R4 Output Divider Register 76. Multisynth4 Parameters BitRegister 77. Multisynth4 Parameters Bit MS4P31916 MS4P21916 Register 78. Multisynth4 Parameters Bit Name MS4P170MS5P370 Register 81. Multisynth4 Parameters BitMS4P270 MS5P3158R5 Output Divider Register 84. Multisynth5 Parameters BitRegister 85. Multisynth5 Parameters Bit MS5P31916 MS5P21916 Register 86. Multisynth5 Parameters Bit Name MS5P170MS7P170 Register 89. Multisynth5 Parameters BitMS5P270 MS6P170R7 Output Divider Register 92. Clock 6 and 7 Output Divider BitR6 Output Divider Clock 1 Initial Phase Offset Register 165. CLK0 Initial Phase OffsetClock 0 Initial Phase Offset Register 166. CLK1 Initial Phase OffsetClock 4 Initial Phase Offset Register 168. CLK3 Initial Phase OffsetClock 3 Initial Phase Offset Register 169. CLK4 Initial Phase OffsetRegister 183. Crystal Internal Load Capacitance Register 177. PLL ResetPLLBReset PLLAResetSi5351A Pin Descriptions Si5351A Pin Descriptions 20-Pin QFN, 24-Pin QsopPin Name Pin Number Pin Type Function 20-QFN Si5351B Pin Descriptions 10. Si5351B Pin Descriptions 20-Pin QFN, 24-Pin QsopSi5351C Pin Descriptions 11. Si5351C Pin Descriptions 20-Pin QFN, 24-Pin QsopNumber 12. Si5351A Pin Descriptions 10-Pin MsopSi5351A 10-MSOP Pin Descriptions PinDevice Part Numbers Ordering Information Si5351XDimension Min Nom Max Qsop Package DimensionsPackage Outline 24-Pin Qsop Dimension Min Nom Package DimensionsPackage Outline 20-Pin QFN Ddd Package Outline 10-Pin MsopRevision 0.9 to Revision Revision 0.1 to RevisionSi5351A/B/C Contact Information

SI5351A/B/C specifications

Silicon Laboratories SI5351A/B/C is a versatile, low-power clock generator and frequency synthesizer that has gained widespread popularity in various applications, including telecommunications, consumer electronics, and industrial control systems. These devices are primarily designed to provide precise clock frequency generation with low phase noise and jitter, making them ideal for high-performance applications.

One of the standout features of the SI5351 is its ability to generate multiple output frequencies simultaneously. Capable of producing up to three independent programmable outputs, the SI5351A/B/C can generate frequencies ranging from 8 kHz to 160 MHz. With its integrated phase-locked loop (PLL) technology, it achieves excellent frequency stability and accuracy, simplifying the design of frequency-dependent systems.

The device operates under a supply voltage range of 1.8V to 3.6V, allowing it to be used in battery-powered applications without excessive power consumption. The SI5351’s low current draw, typically as low as 25 mA, is especially beneficial in portable devices, extending battery life and enhancing overall efficiency. Furthermore, it features a programmable output driver, which can be set to various drive strengths, ensuring compatibility with a wide array of load requirements.

Configuration and control of the SI5351 are user-friendly, implemented via an I2C interface. This allows for straightforward integration into microcontroller-based designs. Moreover, the device includes an on-chip memory that stores settings, which streamlines the reconfiguration process when power cycling, minimizing setup time for developers.

Another significant advantage of the SI5351A/B/C is its output jitter performance, which is typically below 1 ps, resulting in clean output signals essential for high-speed data communications and precise timing applications. The SI5351’s integration of multiple synthesizer stages contributes to its impressive phase noise characteristics, making it suitable for demanding RF applications.

Additionally, the SI5351 devices offer programmable frequency stepping, allowing users to define custom frequency increments, which is particularly useful in applications requiring precise tuning or modulation. This flexibility, combined with its compact size and simple interface, makes the SI5351A/B/C an ideal choice for engineers seeking a reliable, cost-effective solution for generating clock signals in a myriad of electronic systems.

In summary, Silicon Laboratories SI5351A/B/C provides a robust, low-power solution for high-precision clock generation, characterized by its programmable outputs, low jitter, easy configurability, and broad frequency range, making it an excellent choice for both commercial and industrial applications across various sectors.
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