Silicon Laboratories SI5351A/B/C Register 46. Multisynth0 Parameters Bit, MS0P170, MS0P2158

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Si5351A/B/C

Register 46. Multisynth0 Parameters

 

Bit

 

D7

 

D6

 

D5

D4

 

D3

 

D2

 

D1

 

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

MS0_P1[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset value

= xxxx xxxx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

Name

 

 

 

 

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7:0

 

 

MS0_P1[7:0]

Multisynth0 Parameter 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This 18-bit number is an encoded representation of the integer part of the

 

 

 

 

 

 

 

 

MultiSynth1 divider.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register 47. Multisynth0 Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

D7

 

D6

 

D5

D4

 

D3

 

D2

 

D1

 

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

MS0_P3[19:16]

 

 

 

 

MS0_P2[19:16]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

 

 

R/W

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset value

= xxxx xxxx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

Name

 

 

 

 

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7:4

 

MS0_P3[19:16]

Multisynth0 Parameter 3.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This 20-bit number is an encoded representation of the denominator for the frac-

 

 

 

 

 

 

tional part of the MultiSynth0 Divider

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3:0

 

MS0_P2[19:16]

Multisynth0 Parameter 2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This 20-bit number is an encoded representation of the numerator for the fractional

 

 

 

 

 

 

part of the MultiSynth1 Divider.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register 48. Multisynth0 Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

D7

 

D6

 

D5

D4

 

D3

 

D2

 

D1

 

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

 

 

 

 

 

MS0_P2[15:8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset value

= xxxx xxxx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

Name

 

 

 

 

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7:0

 

 

MS0_P2[15:8]

Multisynth0 Parameter 2.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This 20-bit number is an encoded representation of the numerator for the fractional

 

 

 

 

 

 

part of the MultiSynth1 Divider.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Preliminary Rev. 0.95

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Contents Functional Block Diagram FeaturesApplications DescriptionSi5351A/B/C Table of Contents DC Characteristics Electrical SpecificationsParameter Symbol Test Condition Min Typ Max Unit Recommended Operating ConditionsInput Clock Characteristics AC CharacteristicsVcxo Specifications Si5351B only Parameter Symbol Test Condition Min Typ Max UnitsCrystal Requirements1,2 Output Clock CharacteristicsParameter Symbol Min Typ Max Unit Parameter Symbol Test Condition Package Value Unit I2C Specifications SCL,SDA1Thermal Characteristics Absolute Maximum Ratings1 Parameter Symbol Test Condition Value UnitBlock Diagrams of 3-Output and 8-Output Si5351A Devices Detailed Block DiagramsBlock Diagrams of Si5351B and Si5351C 8-Output Devices Crystal Inputs XA, XB Functional DescriptionInput Stage Output Stage Synthesis StagesExternal Clock Input Clkin Voltage Control Input VCOutput Enable OEB Control Pins OEB, SsenSpread Spectrum Enable SSEN-Si5351A and Si5351B only Spread SpectrumI2C Interface I2C and Control SignalsI2C Write Operation Power-Up Configuring the Si5351Writing a Custom Configuration to RAM I2C Programming Procedure Replacing Crystals and Crystal Oscillators Si5351 Application ExamplesReplacing Crystals, Crystal Oscillators, and PLLs Replacing Crystals, Crystal Oscillators, and VCXOsSi5351B Si5351CHcsl Compatible Outputs Replacing a Crystal with a ClockDesign Considerations Trace Characteristics Register Register Map SummaryCLK0PHOFF70 Register Descriptions Register 1. Interrupt Status Sticky Clkin Loss Of Signal Sticky Bit Si5351C OnlySystem Calibration Status Sticky Bit Pllb Loss Of Lock Status Sticky BitRegister 2. Interrupt Status Mask Clkin Loss Of Signal Mask Si5351C OnlySystem Initialization Status Mask Pllb Loss Of Lock Status MaskOutput Disable for CLKx Register 3. Output Enable ControlRegister 9. OEB Pin Enable Control OEB pin enable control of CLKxPllbsrc Register 15. PLL Input SourceMultiSynth 0 Integer Mode Clock 0 Power DownRegister 16. CLK0 Control Bit Name FunctionMultiSynth 1 Integer Mode Clock 1 Power DownRegister 17. CLK1 Control MultiSynth Source Select for CLK1MultiSynth 2 Integer Mode Clock 2 Power DownRegister 18. CLK2 Control MultiSynth Source Select for CLK2MultiSynth 3 Integer Mode Clock 3 Power DownRegister 19. CLK3 Control MultiSynth Source Select for CLK3MultiSynth 4 Integer Mode Clock 4 Power DownRegister 20. CLK4 Control MultiSynth Source Select for CLK4MultiSynth 5 Integer Mode Clock 5 Power DownRegister 21. CLK5 Control MultiSynth Source Select for CLK5FBA MultiSynth Integer Mode Clock 7 Power DownRegister 22. CLK6 Control MultiSynth Source Select for CLK6Register 23. CLK7 Control FBB MultiSynth Integer ModeMultiSynth Source Select for CLK7 Output Clock 7 InvertBit Name Function CLKxDISSTATE Clock x Disable State Register 24. CLK3-0 Disable StateRegister 25. CLK7-4 Disable State Clock x Disable StateMS0P370 MS0P3158 Type Reset valueRegister 42. Multisynth0 Parameters Bit Register 45. Multisynth0 Parameters Bit Register 44. Multisynth0 Parameters BitR0 Output Divider MS0P170 Register 46. Multisynth0 Parameters BitMS0P31916 MS0P21916 MS0P2158MS0P270 Register 49. Multisynth0 Parameters BitMS1P3158 MS1P370Register 53. Multisynth1 Parameters Bit Register 52. Multisynth1 Parameters BitR1 Output Divider MS1P31916 MS1P21916 Register 54. Multisynth1 Parameters Bit Name MS1P170MS1P270 Register 57. Multisynth1 Parameters BitR2 Output Divider Register 60. Multisynth2 Parameters BitMultisynth2 Parameter Register 61. Multisynth2 Parameters BitMS2P31916 MS2P21916 Register 62. Multisynth2 Parameters Bit Name MS2P170MS2P270 Register 65. Multisynth2 Parameters BitMS3P3158 MS3P370Register 69. Multisynth3 Parameters Bit Register 68. Multisynth3 Parameters BitR3 Output Divider MS3P31916 MS3P21916 Register 70. Multisynth3 Parameters Bit Name MS3P170MS3P270 Register 73. Multisynth3 Parameters BitMS4P3158 MS4P370Register 77. Multisynth4 Parameters Bit Register 76. Multisynth4 Parameters BitR4 Output Divider MS4P31916 MS4P21916 Register 78. Multisynth4 Parameters Bit Name MS4P170MS4P270 Register 81. Multisynth4 Parameters BitMS5P3158 MS5P370Register 85. Multisynth5 Parameters Bit Register 84. Multisynth5 Parameters BitR5 Output Divider MS5P31916 MS5P21916 Register 86. Multisynth5 Parameters Bit Name MS5P170MS5P270 Register 89. Multisynth5 Parameters BitMS6P170 MS7P170R6 Output Divider Register 92. Clock 6 and 7 Output Divider BitR7 Output Divider Clock 0 Initial Phase Offset Register 165. CLK0 Initial Phase OffsetRegister 166. CLK1 Initial Phase Offset Clock 1 Initial Phase OffsetClock 3 Initial Phase Offset Register 168. CLK3 Initial Phase OffsetRegister 169. CLK4 Initial Phase Offset Clock 4 Initial Phase OffsetPLLBReset Register 177. PLL ResetPLLAReset Register 183. Crystal Internal Load CapacitancePin Name Pin Number Pin Type Function 20-QFN Si5351A Pin Descriptions 20-Pin QFN, 24-Pin QsopSi5351A Pin Descriptions Si5351B Pin Descriptions 10. Si5351B Pin Descriptions 20-Pin QFN, 24-Pin QsopSi5351C Pin Descriptions 11. Si5351C Pin Descriptions 20-Pin QFN, 24-Pin QsopSi5351A 10-MSOP Pin Descriptions 12. Si5351A Pin Descriptions 10-Pin MsopPin NumberDevice Part Numbers Ordering Information Si5351XPackage Outline 24-Pin Qsop Qsop Package DimensionsDimension Min Nom Max Package Outline 20-Pin QFN Package DimensionsDimension Min Nom Ddd Package Outline 10-Pin MsopRevision 0.9 to Revision Revision 0.1 to RevisionSi5351A/B/C Contact Information

SI5351A/B/C specifications

Silicon Laboratories SI5351A/B/C is a versatile, low-power clock generator and frequency synthesizer that has gained widespread popularity in various applications, including telecommunications, consumer electronics, and industrial control systems. These devices are primarily designed to provide precise clock frequency generation with low phase noise and jitter, making them ideal for high-performance applications.

One of the standout features of the SI5351 is its ability to generate multiple output frequencies simultaneously. Capable of producing up to three independent programmable outputs, the SI5351A/B/C can generate frequencies ranging from 8 kHz to 160 MHz. With its integrated phase-locked loop (PLL) technology, it achieves excellent frequency stability and accuracy, simplifying the design of frequency-dependent systems.

The device operates under a supply voltage range of 1.8V to 3.6V, allowing it to be used in battery-powered applications without excessive power consumption. The SI5351’s low current draw, typically as low as 25 mA, is especially beneficial in portable devices, extending battery life and enhancing overall efficiency. Furthermore, it features a programmable output driver, which can be set to various drive strengths, ensuring compatibility with a wide array of load requirements.

Configuration and control of the SI5351 are user-friendly, implemented via an I2C interface. This allows for straightforward integration into microcontroller-based designs. Moreover, the device includes an on-chip memory that stores settings, which streamlines the reconfiguration process when power cycling, minimizing setup time for developers.

Another significant advantage of the SI5351A/B/C is its output jitter performance, which is typically below 1 ps, resulting in clean output signals essential for high-speed data communications and precise timing applications. The SI5351’s integration of multiple synthesizer stages contributes to its impressive phase noise characteristics, making it suitable for demanding RF applications.

Additionally, the SI5351 devices offer programmable frequency stepping, allowing users to define custom frequency increments, which is particularly useful in applications requiring precise tuning or modulation. This flexibility, combined with its compact size and simple interface, makes the SI5351A/B/C an ideal choice for engineers seeking a reliable, cost-effective solution for generating clock signals in a myriad of electronic systems.

In summary, Silicon Laboratories SI5351A/B/C provides a robust, low-power solution for high-precision clock generation, characterized by its programmable outputs, low jitter, easy configurability, and broad frequency range, making it an excellent choice for both commercial and industrial applications across various sectors.
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