Silicon Laboratories SI5351A/B/C specifications Register 20. CLK4 Control, Clock 4 Power Down

Page 34

Si5351A/B/C

Register 20. CLK4 Control

Bit

 

D7

 

D6

 

D5

D4

 

D3

 

D2

D1

 

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

CLK4_PDN

MS4_INT

MS4_SRC

CLK4_INV

 

CLK4_SRC[1:0]

CLK4_IDRV[1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Type

 

R/W

R/W

R/W

R/W

R/W

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset value = 0000 0000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

Name

 

 

 

 

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

CLK4_PDN

Clock 4 Power Down.

 

 

 

 

 

 

 

 

 

 

 

This bit allows powering down the CLK4 output driver to conserve power when the out-

 

 

 

 

 

put is unused.

 

 

 

 

 

 

 

 

 

 

 

 

 

0: CLK4 is powered up.

 

 

 

 

 

 

 

 

 

 

 

1: CLK4 is powered down.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

MS4_INT

MultiSynth 4 Integer Mode.

 

 

 

 

 

 

 

 

 

 

 

This bit can be used to force MS4 into Integer mode to improve jitter performance.

 

 

 

 

 

Note that the fractional mode is necessary when a delay offset is specified for CLK4.

 

 

 

 

 

0: MS4 operates in fractional division mode.

 

 

 

 

 

 

 

 

 

1: MS4 operates in integer mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5

 

 

MS4_SRC

MultiSynth Source Select for CLK4.

 

 

 

 

 

 

 

 

 

 

 

0: Select PLLA as the source for MultiSynth0.

 

 

 

 

 

 

 

 

 

1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

CLK4_INV

Output Clock 4 Invert.

 

 

 

 

 

 

 

 

 

 

 

0: Output Clock 4 is not inverted.

 

 

 

 

 

 

 

 

 

 

 

1: Output Clock 4 is inverted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3:2

 

CLK4_SRC[1:0]

Output Clock 4 Input Source.

 

 

 

 

 

 

 

 

 

 

 

These bits determine the input source for CLK4.

 

 

 

 

 

 

 

 

 

00: Select the XTAL as the clock source for CLK4. This option by-passes both synthe-

 

 

 

 

 

sis stages (PLL/VCXO & MultiSynth) and connects CLK4 directly to the oscillator

 

 

 

 

 

which generates an output frequency determined by the XTAL frequency.

 

 

 

 

 

 

01: Select CLKIN as the clock source for CLK4. This by-passes both synthesis stages

 

 

 

 

 

(PLL/VCXO & MultiSynth) and connects CLK4 directly to the CLKIN input. This essen-

 

 

 

 

 

tially creates a buffered output of the CLKIN input.

 

 

 

 

 

 

 

 

 

10: Reserved. Do not select this option.

 

 

 

 

 

 

 

 

 

11: Select MultiSynth 0 as the source for CLK4. Select this option when using the

 

 

 

 

 

Si5351 to generate free-running or synchronous clocks.

 

 

 

 

 

 

 

 

 

 

1:0

 

CLK4_IDRV[1:0]

CLK4 Output Rise and Fall time / Drive Strength Control.

 

 

 

 

 

 

 

 

00: 2 mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

01: 4 mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10: 6 mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11: 8 mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

34

Preliminary Rev. 0.95

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Contents Applications FeaturesFunctional Block Diagram DescriptionSi5351A/B/C Table of Contents Parameter Symbol Test Condition Min Typ Max Unit Electrical SpecificationsDC Characteristics Recommended Operating ConditionsVcxo Specifications Si5351B only AC CharacteristicsInput Clock Characteristics Parameter Symbol Test Condition Min Typ Max UnitsParameter Symbol Min Typ Max Unit Output Clock CharacteristicsCrystal Requirements1,2 Thermal Characteristics I2C Specifications SCL,SDA1Parameter Symbol Test Condition Package Value Unit Parameter Symbol Test Condition Value Unit Absolute Maximum Ratings1Detailed Block Diagrams Block Diagrams of 3-Output and 8-Output Si5351A DevicesBlock Diagrams of Si5351B and Si5351C 8-Output Devices Input Stage Functional DescriptionCrystal Inputs XA, XB External Clock Input Clkin Synthesis StagesOutput Stage Voltage Control Input VCSpread Spectrum Enable SSEN-Si5351A and Si5351B only Control Pins OEB, SsenOutput Enable OEB Spread SpectrumI2C and Control Signals I2C InterfaceI2C Write Operation Writing a Custom Configuration to RAM Configuring the Si5351Power-Up I2C Programming Procedure Si5351 Application Examples Replacing Crystals and Crystal OscillatorsSi5351B Replacing Crystals, Crystal Oscillators, and VCXOsReplacing Crystals, Crystal Oscillators, and PLLs Si5351CReplacing a Crystal with a Clock Hcsl Compatible OutputsDesign Considerations Trace Characteristics Register Map Summary RegisterCLK0PHOFF70 Register Descriptions System Calibration Status Sticky Bit Clkin Loss Of Signal Sticky Bit Si5351C OnlyRegister 1. Interrupt Status Sticky Pllb Loss Of Lock Status Sticky BitSystem Initialization Status Mask Clkin Loss Of Signal Mask Si5351C OnlyRegister 2. Interrupt Status Mask Pllb Loss Of Lock Status MaskRegister 9. OEB Pin Enable Control Register 3. Output Enable ControlOutput Disable for CLKx OEB pin enable control of CLKxRegister 15. PLL Input Source PllbsrcRegister 16. CLK0 Control Clock 0 Power DownMultiSynth 0 Integer Mode Bit Name FunctionRegister 17. CLK1 Control Clock 1 Power DownMultiSynth 1 Integer Mode MultiSynth Source Select for CLK1Register 18. CLK2 Control Clock 2 Power DownMultiSynth 2 Integer Mode MultiSynth Source Select for CLK2Register 19. CLK3 Control Clock 3 Power DownMultiSynth 3 Integer Mode MultiSynth Source Select for CLK3Register 20. CLK4 Control Clock 4 Power DownMultiSynth 4 Integer Mode MultiSynth Source Select for CLK4Register 21. CLK5 Control Clock 5 Power DownMultiSynth 5 Integer Mode MultiSynth Source Select for CLK5Register 22. CLK6 Control Clock 7 Power DownFBA MultiSynth Integer Mode MultiSynth Source Select for CLK6MultiSynth Source Select for CLK7 FBB MultiSynth Integer ModeRegister 23. CLK7 Control Output Clock 7 InvertRegister 25. CLK7-4 Disable State Register 24. CLK3-0 Disable StateBit Name Function CLKxDISSTATE Clock x Disable State Clock x Disable StateRegister 42. Multisynth0 Parameters Bit MS0P3158 Type Reset valueMS0P370 R0 Output Divider Register 44. Multisynth0 Parameters BitRegister 45. Multisynth0 Parameters Bit MS0P31916 MS0P21916 Register 46. Multisynth0 Parameters BitMS0P170 MS0P2158MS1P3158 Register 49. Multisynth0 Parameters BitMS0P270 MS1P370R1 Output Divider Register 52. Multisynth1 Parameters BitRegister 53. Multisynth1 Parameters Bit Register 54. Multisynth1 Parameters Bit Name MS1P170 MS1P31916 MS1P21916Register 57. Multisynth1 Parameters Bit MS1P270Multisynth2 Parameter Register 60. Multisynth2 Parameters BitR2 Output Divider Register 61. Multisynth2 Parameters BitRegister 62. Multisynth2 Parameters Bit Name MS2P170 MS2P31916 MS2P21916MS3P3158 Register 65. Multisynth2 Parameters BitMS2P270 MS3P370R3 Output Divider Register 68. Multisynth3 Parameters BitRegister 69. Multisynth3 Parameters Bit Register 70. Multisynth3 Parameters Bit Name MS3P170 MS3P31916 MS3P21916MS4P3158 Register 73. Multisynth3 Parameters BitMS3P270 MS4P370R4 Output Divider Register 76. Multisynth4 Parameters BitRegister 77. Multisynth4 Parameters Bit Register 78. Multisynth4 Parameters Bit Name MS4P170 MS4P31916 MS4P21916MS5P3158 Register 81. Multisynth4 Parameters BitMS4P270 MS5P370R5 Output Divider Register 84. Multisynth5 Parameters BitRegister 85. Multisynth5 Parameters Bit Register 86. Multisynth5 Parameters Bit Name MS5P170 MS5P31916 MS5P21916MS6P170 Register 89. Multisynth5 Parameters BitMS5P270 MS7P170R7 Output Divider Register 92. Clock 6 and 7 Output Divider BitR6 Output Divider Register 166. CLK1 Initial Phase Offset Register 165. CLK0 Initial Phase OffsetClock 0 Initial Phase Offset Clock 1 Initial Phase OffsetRegister 169. CLK4 Initial Phase Offset Register 168. CLK3 Initial Phase OffsetClock 3 Initial Phase Offset Clock 4 Initial Phase OffsetPLLAReset Register 177. PLL ResetPLLBReset Register 183. Crystal Internal Load CapacitanceSi5351A Pin Descriptions Si5351A Pin Descriptions 20-Pin QFN, 24-Pin QsopPin Name Pin Number Pin Type Function 20-QFN 10. Si5351B Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351B Pin Descriptions11. Si5351C Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351C Pin DescriptionsPin 12. Si5351A Pin Descriptions 10-Pin MsopSi5351A 10-MSOP Pin Descriptions NumberOrdering Information Si5351X Device Part NumbersDimension Min Nom Max Qsop Package DimensionsPackage Outline 24-Pin Qsop Dimension Min Nom Package DimensionsPackage Outline 20-Pin QFN Package Outline 10-Pin Msop DddRevision 0.1 to Revision Revision 0.9 to RevisionSi5351A/B/C Contact Information

SI5351A/B/C specifications

Silicon Laboratories SI5351A/B/C is a versatile, low-power clock generator and frequency synthesizer that has gained widespread popularity in various applications, including telecommunications, consumer electronics, and industrial control systems. These devices are primarily designed to provide precise clock frequency generation with low phase noise and jitter, making them ideal for high-performance applications.

One of the standout features of the SI5351 is its ability to generate multiple output frequencies simultaneously. Capable of producing up to three independent programmable outputs, the SI5351A/B/C can generate frequencies ranging from 8 kHz to 160 MHz. With its integrated phase-locked loop (PLL) technology, it achieves excellent frequency stability and accuracy, simplifying the design of frequency-dependent systems.

The device operates under a supply voltage range of 1.8V to 3.6V, allowing it to be used in battery-powered applications without excessive power consumption. The SI5351’s low current draw, typically as low as 25 mA, is especially beneficial in portable devices, extending battery life and enhancing overall efficiency. Furthermore, it features a programmable output driver, which can be set to various drive strengths, ensuring compatibility with a wide array of load requirements.

Configuration and control of the SI5351 are user-friendly, implemented via an I2C interface. This allows for straightforward integration into microcontroller-based designs. Moreover, the device includes an on-chip memory that stores settings, which streamlines the reconfiguration process when power cycling, minimizing setup time for developers.

Another significant advantage of the SI5351A/B/C is its output jitter performance, which is typically below 1 ps, resulting in clean output signals essential for high-speed data communications and precise timing applications. The SI5351’s integration of multiple synthesizer stages contributes to its impressive phase noise characteristics, making it suitable for demanding RF applications.

Additionally, the SI5351 devices offer programmable frequency stepping, allowing users to define custom frequency increments, which is particularly useful in applications requiring precise tuning or modulation. This flexibility, combined with its compact size and simple interface, makes the SI5351A/B/C an ideal choice for engineers seeking a reliable, cost-effective solution for generating clock signals in a myriad of electronic systems.

In summary, Silicon Laboratories SI5351A/B/C provides a robust, low-power solution for high-precision clock generation, characterized by its programmable outputs, low jitter, easy configurability, and broad frequency range, making it an excellent choice for both commercial and industrial applications across various sectors.
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