Silicon Laboratories SI5351A/B/C specifications I2C Interface, I2C and Control Signals

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Si5351A/B/C

4. I2C Interface

Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the I2C interface. The following is a list of the common features that are controllable through the I2C interface. A summary of register functions is shown in Section 7.

Read Status Indicators

Loss of signal (LOS) for the CLKIN input Loss of lock (LOL) for PLLA and PLLB

Configuration of multiplication and divider values for the PLLs, MultiSynth dividers

Configuration of the Spread Spectrum profile (down or center spread, modulation percentage)

Control of the cross point switch selection for each of the PLLs and MultiSynth dividers

Set output clock options

Enable/disable for each clock output Invert/non-invert for each clock output Output divider values (2n, n=1.. 7)

Output state when disabled (stop hi, stop low, Hi-Z) Output phase offset

The I2C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.

The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7. Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the I2C specification.

 

VDD

>1k

>1k

 

Si5351

 

SCL

I2C Bus

SDA

 

4.7 k

INTR

 

I2C Address Select:

A0

Pull-up to VDD (A0 = 1)

 

Pull-down to GND (A0 = 0)

 

Figure 7. I2C and Control Signals

The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that require more than one Si5351 on a single I2C bus.

Slave Address

6

5

4

3

2

1

0

 

 

 

 

 

 

 

1

1

0

0

0

0

0/1

 

 

 

 

 

 

 

A0

Figure 8. Si5351 I2C Slave Address

Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7- bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write burst operation is also shown where every additional data word is written using to an auto-incremented address.

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Preliminary Rev. 0.95

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Contents Applications FeaturesFunctional Block Diagram DescriptionSi5351A/B/C Table of Contents Parameter Symbol Test Condition Min Typ Max Unit Electrical SpecificationsDC Characteristics Recommended Operating ConditionsVcxo Specifications Si5351B only AC CharacteristicsInput Clock Characteristics Parameter Symbol Test Condition Min Typ Max UnitsCrystal Requirements1,2 Output Clock CharacteristicsParameter Symbol Min Typ Max Unit Parameter Symbol Test Condition Package Value Unit I2C Specifications SCL,SDA1Thermal Characteristics Parameter Symbol Test Condition Value Unit Absolute Maximum Ratings1Detailed Block Diagrams Block Diagrams of 3-Output and 8-Output Si5351A DevicesBlock Diagrams of Si5351B and Si5351C 8-Output Devices Crystal Inputs XA, XB Functional DescriptionInput Stage External Clock Input Clkin Synthesis StagesOutput Stage Voltage Control Input VCSpread Spectrum Enable SSEN-Si5351A and Si5351B only Control Pins OEB, SsenOutput Enable OEB Spread SpectrumI2C and Control Signals I2C InterfaceI2C Write Operation Power-Up Configuring the Si5351Writing a Custom Configuration to RAM I2C Programming Procedure Si5351 Application Examples Replacing Crystals and Crystal OscillatorsSi5351B Replacing Crystals, Crystal Oscillators, and VCXOsReplacing Crystals, Crystal Oscillators, and PLLs Si5351CReplacing a Crystal with a Clock Hcsl Compatible OutputsDesign Considerations Trace Characteristics Register Map Summary RegisterCLK0PHOFF70 Register Descriptions System Calibration Status Sticky Bit Clkin Loss Of Signal Sticky Bit Si5351C OnlyRegister 1. Interrupt Status Sticky Pllb Loss Of Lock Status Sticky BitSystem Initialization Status Mask Clkin Loss Of Signal Mask Si5351C OnlyRegister 2. Interrupt Status Mask Pllb Loss Of Lock Status MaskRegister 9. OEB Pin Enable Control Register 3. Output Enable ControlOutput Disable for CLKx OEB pin enable control of CLKxRegister 15. PLL Input Source PllbsrcRegister 16. CLK0 Control Clock 0 Power DownMultiSynth 0 Integer Mode Bit Name FunctionRegister 17. CLK1 Control Clock 1 Power DownMultiSynth 1 Integer Mode MultiSynth Source Select for CLK1Register 18. CLK2 Control Clock 2 Power DownMultiSynth 2 Integer Mode MultiSynth Source Select for CLK2Register 19. CLK3 Control Clock 3 Power DownMultiSynth 3 Integer Mode MultiSynth Source Select for CLK3Register 20. CLK4 Control Clock 4 Power DownMultiSynth 4 Integer Mode MultiSynth Source Select for CLK4Register 21. CLK5 Control Clock 5 Power DownMultiSynth 5 Integer Mode MultiSynth Source Select for CLK5Register 22. CLK6 Control Clock 7 Power DownFBA MultiSynth Integer Mode MultiSynth Source Select for CLK6MultiSynth Source Select for CLK7 FBB MultiSynth Integer ModeRegister 23. CLK7 Control Output Clock 7 InvertRegister 25. CLK7-4 Disable State Register 24. CLK3-0 Disable StateBit Name Function CLKxDISSTATE Clock x Disable State Clock x Disable StateMS0P370 MS0P3158 Type Reset valueRegister 42. Multisynth0 Parameters Bit Register 45. Multisynth0 Parameters Bit Register 44. Multisynth0 Parameters BitR0 Output Divider MS0P31916 MS0P21916 Register 46. Multisynth0 Parameters BitMS0P170 MS0P2158MS1P3158 Register 49. Multisynth0 Parameters BitMS0P270 MS1P370Register 53. Multisynth1 Parameters Bit Register 52. Multisynth1 Parameters BitR1 Output Divider Register 54. Multisynth1 Parameters Bit Name MS1P170 MS1P31916 MS1P21916Register 57. Multisynth1 Parameters Bit MS1P270Multisynth2 Parameter Register 60. Multisynth2 Parameters BitR2 Output Divider Register 61. Multisynth2 Parameters BitRegister 62. Multisynth2 Parameters Bit Name MS2P170 MS2P31916 MS2P21916MS3P3158 Register 65. Multisynth2 Parameters BitMS2P270 MS3P370Register 69. Multisynth3 Parameters Bit Register 68. Multisynth3 Parameters BitR3 Output Divider Register 70. Multisynth3 Parameters Bit Name MS3P170 MS3P31916 MS3P21916MS4P3158 Register 73. Multisynth3 Parameters BitMS3P270 MS4P370Register 77. Multisynth4 Parameters Bit Register 76. Multisynth4 Parameters BitR4 Output Divider Register 78. Multisynth4 Parameters Bit Name MS4P170 MS4P31916 MS4P21916MS5P3158 Register 81. Multisynth4 Parameters BitMS4P270 MS5P370Register 85. Multisynth5 Parameters Bit Register 84. Multisynth5 Parameters BitR5 Output Divider Register 86. Multisynth5 Parameters Bit Name MS5P170 MS5P31916 MS5P21916MS6P170 Register 89. Multisynth5 Parameters BitMS5P270 MS7P170R6 Output Divider Register 92. Clock 6 and 7 Output Divider BitR7 Output Divider Register 166. CLK1 Initial Phase Offset Register 165. CLK0 Initial Phase OffsetClock 0 Initial Phase Offset Clock 1 Initial Phase OffsetRegister 169. CLK4 Initial Phase Offset Register 168. CLK3 Initial Phase OffsetClock 3 Initial Phase Offset Clock 4 Initial Phase OffsetPLLAReset Register 177. PLL ResetPLLBReset Register 183. Crystal Internal Load CapacitancePin Name Pin Number Pin Type Function 20-QFN Si5351A Pin Descriptions 20-Pin QFN, 24-Pin QsopSi5351A Pin Descriptions 10. Si5351B Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351B Pin Descriptions11. Si5351C Pin Descriptions 20-Pin QFN, 24-Pin Qsop Si5351C Pin DescriptionsPin 12. Si5351A Pin Descriptions 10-Pin MsopSi5351A 10-MSOP Pin Descriptions NumberOrdering Information Si5351X Device Part NumbersPackage Outline 24-Pin Qsop Qsop Package DimensionsDimension Min Nom Max Package Outline 20-Pin QFN Package DimensionsDimension Min Nom Package Outline 10-Pin Msop DddRevision 0.1 to Revision Revision 0.9 to RevisionSi5351A/B/C Contact Information

SI5351A/B/C specifications

Silicon Laboratories SI5351A/B/C is a versatile, low-power clock generator and frequency synthesizer that has gained widespread popularity in various applications, including telecommunications, consumer electronics, and industrial control systems. These devices are primarily designed to provide precise clock frequency generation with low phase noise and jitter, making them ideal for high-performance applications.

One of the standout features of the SI5351 is its ability to generate multiple output frequencies simultaneously. Capable of producing up to three independent programmable outputs, the SI5351A/B/C can generate frequencies ranging from 8 kHz to 160 MHz. With its integrated phase-locked loop (PLL) technology, it achieves excellent frequency stability and accuracy, simplifying the design of frequency-dependent systems.

The device operates under a supply voltage range of 1.8V to 3.6V, allowing it to be used in battery-powered applications without excessive power consumption. The SI5351’s low current draw, typically as low as 25 mA, is especially beneficial in portable devices, extending battery life and enhancing overall efficiency. Furthermore, it features a programmable output driver, which can be set to various drive strengths, ensuring compatibility with a wide array of load requirements.

Configuration and control of the SI5351 are user-friendly, implemented via an I2C interface. This allows for straightforward integration into microcontroller-based designs. Moreover, the device includes an on-chip memory that stores settings, which streamlines the reconfiguration process when power cycling, minimizing setup time for developers.

Another significant advantage of the SI5351A/B/C is its output jitter performance, which is typically below 1 ps, resulting in clean output signals essential for high-speed data communications and precise timing applications. The SI5351’s integration of multiple synthesizer stages contributes to its impressive phase noise characteristics, making it suitable for demanding RF applications.

Additionally, the SI5351 devices offer programmable frequency stepping, allowing users to define custom frequency increments, which is particularly useful in applications requiring precise tuning or modulation. This flexibility, combined with its compact size and simple interface, makes the SI5351A/B/C an ideal choice for engineers seeking a reliable, cost-effective solution for generating clock signals in a myriad of electronic systems.

In summary, Silicon Laboratories SI5351A/B/C provides a robust, low-power solution for high-precision clock generation, characterized by its programmable outputs, low jitter, easy configurability, and broad frequency range, making it an excellent choice for both commercial and industrial applications across various sectors.
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