![](/images/new-backgrounds/1192644/19264473x1.webp)
AT INTERFACE DESCRIPTION
Ultra DMA Timing
TIMING PARAMETERS (all times in nanoseconds) | MODE 0 | MODE 1 | MODE 2 | ||||
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| MIN | MAX | MIN | MAX | MIN | MAX |
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tCYC | Cycle Time (from STROBE edge to STROBE edge) | 114 |
| 75 |
| 55 |
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t2CYC | Two cycle time (from rising edge to next rising edge or | 235 |
| 156 |
| 117 |
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| from falling edge to next falling edge of STROBE) |
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tDS | Data setup time (at recipient) | 15 |
| 10 |
| 7 | 70 |
tDH | Data hold time (at recipient) | 5 |
| 5 |
| 5 |
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tDVS | Data valid setup time at sender (time from data bus being | 70 |
| 48 |
| 34 | 5 |
| valid until STROBE edge) |
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tDVH | Data valid hold time at sender (time from STROBE edge | 6 |
| 6 |
| 6 | 20 |
| until data may go invalid) |
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tFS | First STROBE (time for device to send first STROBE) | 0 | 230 | 0 | 200 | 0 | 170 |
tLI | Limited interlock time (time allowed between an action by | 0 | 150 | 0 | 150 | 0 | 150 |
| one agent, either host or device, and the following action | ||||||
| by the other agent) |
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tMLI | Interlock time with minimum | 20 |
| 20 |
| 20 |
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tUI | Unlimited interlock time | 0 |
| 0 |
| 0 |
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tAZ | Maximum time allowed for outputs to release |
| 10 |
| 10 |
| 10 |
tZAH | Minimum delay time required for output drivers turning on | 20 |
| 20 |
| 20 |
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tZAD | (from released state) | 0 |
| 0 |
| 0 |
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tENV | Envelope time (all control signal transitions are within the | 20 | 70 | 20 | 70 | 20 | 70 |
| DMACK envelope by this much time) |
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tSR | STROBE to DMARDY (response time to ensure the |
| 50 |
| 30 |
| 20 |
| synchronous pause case when the recipient is pausing) |
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tRFS |
| 75 |
| 60 |
| 50 | |
| be sent this long after receiving DMARDY- negation) |
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tRP | 160 |
| 125 |
| 100 |
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| that the sender has paused after negation of |
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tIORDYZ |
| 20 |
| 20 |
| 20 | |
tZIORDY | Minimum time device shall wait before driving IORDY | 0 |
| 0 |
| 0 |
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tACK | Setup and hold times before assertion and negation of | 20 |
| 20 |
| 20 |
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| DMACK- |
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tSS | Time from STROBE edge to STOP assertion when the | 50 |
| 50 |
| 50 |
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| sender is stopping |
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DMARQ |
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(device) |
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tUI |
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DMACK- |
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(host) |
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tACK | tENV |
STOP |
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(host) |
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tACK | tENV |
HDMARDY- |
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(host) |
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tZIORDY |
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DSTROBE |
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(device) |
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tAZ |
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DD(15:0) |
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tACK |
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DA0, DA1, DA2, |
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tFS
tZAD |
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tFS |
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tZAD |
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tVDS | tDVH |
Figure 5 - 4
Initiating an Ultra DMA Data In Burst
5 – 5