Maxtor 2R010H1, 2R015H1 specifications Control Diagnostic Registers, Por T Ead Wr Ite

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HOST SOFTWARE INTERFACE

Control Diagnostic Registers

These I/O port addresses reference three Control/Diagnostic registers:

I/O POR T	R EAD	WR ITE

3F6h	Alternate Status	F ixed Disk C ontrol

3F7h	D igital Input	Not us ed

Alternate Status Register

Contains the same information as the Status register in the Task File. However, this register may be read at any time without clearing a pending interrupt.

Device Control Register

Contains the software Reset and Enable bit to enable interrupt requests to the host. Bit definitions follow:

7	6	5	4	3	2	1	0

0	0	0	0	0	SRST	IEN	0

					Reset	IRQ Enable

Reset – Setting the software Reset bit holds the drive in the reset state. Clearing the bit re-enables the drive. The software Reset bit must be held active for a minimum of 5 µsec.

IRQ Enable – Setting the Interrupt Request Enable to 0 enables the IRQ 14 signal to the host. When this bit is set to 1, IRQ14 is tri-stated, and interrupts to the host are disabled. Any pending interrupt occurs when the bit is set to 0. The default state of this bit after power up is 0 (interrupt enabled).

Digital Input Register

Contains information about the state of the drive. Bit definitions follow:

7	6	5	4	3	2	1	0

x	-W G	-HS3	-HS2	-HS1	-HS0	- DS1	DS0

Reserved	Write	Head	Head	Head	Head	D rive	D rive
	Gate	Select 3	Select 2	Select 1	Select 0	Select 1	Select 0

Bit 7 of the host data bus is not driven when this register is read.

-Write Gate – Reflects the state of the active low write gate signal on the drive.

-Head Select 3 through -Head Select 0 – Represents the ones complement of the currently selected head number.

-Drive Select 1 – Is 0 if drive 1 selected; 1 otherwise.

-Drive Select 0 – Is 0 if drive 0 selected; 1 otherwise.

6 – 5

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Contents Hard Disk Drive Specifications Models 2R015H1 & 2R010H1 U T I O N Before You BeginContents Handling and Installation Product SpecificationsInterface Commands AT Interface DescriptionHost Software Interface Glossary Service and SupportFigures Abbreviations IntroductionMaxtorCorporation ManualOrganizationConventions Product Description Key FeaturesFunctional / Interface Product FeaturesCacheManagement Major HDA Components SubsystemConfiguration Jumper Location / ConfigurationCylinder Limitation Jumper Description Models and Capacities ProductSpecificationsDrive Configuration PerformanceSpecificationsPhysical Dimensions Environmental Limits PowerRequirementsPower Mode Definitions EPA Energy Star ComplianceShock and Vibration Reliability SpecificationsEMC/EMI Safety Regulatory ComplianceHandlingandInstallation HardDriveHandlingPrecautionsElectro-StaticDischargeESD Multi-pack Shipping Container UnpackingandInspectionRepacking PhysicalInstallationHook up Before You BeginStart up Set upPIN IGN AL InterfaceConnectorATInterfaceDescription PinDescriptionSummaryPin Description Table PIN Name Signal Name Signal Desc RiptionPIO Timing IM in G Paramet ERS ModeDMATiming Imin G Paramet ERS ModeMode Ultra DMA TimingSustained Ultra DMA Data In Burst Device Terminating an Ultra DMA Data In Burst Initiating an Ultra DMA Data Out Burst Device Pausing an Ultra DMA Data Out Burst Device Terminating an Ultra DMA Data Out Burst HostSoftwareInterface Task File RegistersPOR T EAD WR ITE Conten TS LBA Bits Seek, Format, and Diagnostic Commands CommandRegisterM M a N D N a M E M M a N D code PA R a M E T E R S U S E D SummaryControl Diagnostic Registers Reset and Interrupt Handling InterfaceCommands ReadCommands Read DMA WriteCommands Write Multiple ModeSet/CheckCommands VAL UE DES C RIP TionLE VE L VAL UE Omman D Timer VAL UE TIME-OUT Period PowerModeCommandsSleep Mode Or D ENT Desc Ription InitializationCommandsOr D 15- 10, as c urrently defined Initialize Drive Parameters ER ROR Code Desc Ription Seek,FormatandDiagnosticCommandsKey Register A.R.T. CommandSetProduct Support ServiceandSupportService Policy No Quibble ServiceFrom Dial Glossary Character Correctable errorCentral processing unit CPU ChannelError free Direct accessDirect memory access DMA Error correction code ECCGigabyte GB Hard errorHead disk assembly HDA Frequency responseLogical address Late windowLatency LogicRead gate signal Phase locked loop PLLPhase margin Random access memory RAMSoft error Sector pulse signalSeek complete signal Sequential accessWrite gate signal Strobe offset signalUn-correctable error Unrecoverable error