Measurement Specialties CIO-SSH16 user manual Droop Rate, Sample and Hold Timing Diagram

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ANALOG INPUT BOARD’S

ON-BOARD SAMPLE-HOLD

 

 

 

 

 

 

 

 

 

 

CIO-SSH16 SAMPLE MODE

 

 

CIO-SSH16 SAMPLE MODE

 

 

 

CIO-SSH16 HOLDS WHILE ANALOG IN BOARD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LF398 SAMPLE/HOLD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 26

ACQUIRES DATA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4-7. Sample and Hold Timing Diagram

Note that Channel 0 of the CIO-SSH16 does not have an LF398 sample and hold chip. That is because there is one sample and hold on the analog input board and it serves as the S&H chip for CIO-SSH16’s channel 0. When the S&H on the A/D board is sampling the signal on channel 0, the S&Hs on the CIO-SSH16 are sampling the signals on channels 1 to n. When the S&H on the analog input board enters HOLD, all the S&Hs on the CIO-SSH16 enter HOLD. The S&H chips on the CIO-SSH16 will remain in HOLD mode until the analog input board has acquired all of the channels required and channel 0 is again sampled. In this way, signals for up to 16 channels are sampled simultaneously.

4.5 DROOP RATE

Droop rate is the rate at which the output of the sample and hold 'droops' from the value it was in the instant the S&H entered HOLD mode. The specification on the LF398 LVì100 uV/ms.

A droop implies that reading the output of the S&H as quickly as possible is desirable.

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Contents CIO-SSH16 Copyright 2000 Measurement Computing Corp Adding Amplifiers & Sample / Hold Chips This page is blank Hardware Installation Software InstallationIntroduction Power Cable Signal Cable Power ConnectorAnalog Input Board Setup Gain SwitchesSignal Connection Connector DiagramAnalog Inputs Floating DifferentialDifferential ExamplePage Analog Input ArchitectureAmplification CIO-SSH16 vs. Programmable Gain A/D Boards Sample & Hold S15 S16 Sample and Hold Timing Diagram Droop RateResolution Calculation Adding Amplifiers Sample / Hold ChipsRange Calculation Time to Sample CalculationSpecifications Analog input sectionSample / hold section Analog Electronics Voltage DividersPage Common Mode Range Differential & Single Ended InputsPage Ground Loops Common MisunderstandingsLOW Pass Filters A/D Resolution & Engineering Units Converter # VoltsEngineering Units Current Loop 4-20 mANoise Sources of NoiseSignal Wire Noise Sensor NoiseSmoothing Data For your notes EC Declaration of Conformity