Motherboard Description | SY-7ISA+ |
requests on the host bus). Host bus addresses are decoded by the Intel® 815E GMCH for accesses to system memory, PCI memory and PCI I/O (via hub interface), PCI configuration space and Graphics memory. The Intel® 815E GMCH takes advantage of the pipelined addressing capability of the pipelined addressing capability of the processor to improve the overall system performance.
The Intel® 815E GMCH supports the 370-pin socket processor. *370-pin socket (PGA370). The PGA370 is a zero insertion force (ZIF) socket that a processor in the FC-PGA package will use to interface with a system board.
1-6.4 System Memory Interface
The Intel® 815E GMCH integrates a system memory controller that supports a 64-bit 100/133 MHz SDRAM array. The only DRAM type supported is industry standard Synchronous DRAM (SDRAM). The SDRAM controller interface is fully configurable through a set of control registers.
The Intel® 815E GMCH supports industry standard 64-bit wide DIMMs with SDRAM devices. The thirteen multiplexed address lines. SMAA[12:0], along with the two bank select lines, SBS[1:0], allow the Intel® 815E GMCH to support 2M, 4M, 8M, 16M, and 42M x64 DIMM. Only asymmetric addressing is supported. The Intel® 815E GMCH has 6 SCS# lines (2 copies of each for electrical loading), enabling the support of up to six 64-bit rows of SDRAM. The Intel® 815E GMCH targets SDRAM with CL2 and CL3 and supports both single and double-sided DIMMs. Additionally, the Intel® 815E GMCH also provides a 1024 deep refresh queue. The Intel® 815E GMCH can be configured to keep up to 4 page op[en within the memory array. Pages can be kept open in any one bank of memory.
SCKE[4:0] is used in configurations requiring powerdown mode for the SDRAM.
