SOYO SOYOTM manual Bios Features Setup, CPU Internal, Cache, Quick Power, On Self Test

Page 27

BIOS Setup

23

BIOS Features Setup

Run the BIOS Features Setup as follows.

1.Choose ÒBIOS FEATURES SETUPÓ from the Main Menu and a screen with a list of items appears. (The screen below shows the BIOS default settings.)

ROM PCI/ISA BIOS

BIOS FEATURES SETUP

AWARD SOFTWARE, INC.

CPU Internal Cache

: Enabled

Video BIOS Shadow

: Enabled

External Cache

: Enabled

C8000-CBFFF Shadow

: Disabled

Quick Power on Self Test

: Enabled

CC000-CFFFF Shadow

: Disabled

Boot Sequence

: A,C,SCSI

D0000-D3FFF Shadow

: Disabled

Swap Floppy Drive

: Disabled

D4000-D7FFF Shadow

: Disabled

Boot Up NumLock Status

: On

D8000-DBFFF Shadow

: Disabled

Typematic Rate Setting

: Disabled

DC000-DFFFF Shadow

: Disabled

Typematic Rate (Chars/Sec)

: 6

ESC : Quit

− ↓ → ←: Select Item

Typematic Delay (Msec)

: 250

Security Option

: Setup

F1

: Help

PU/PD/+/– : Modify

PCI/VGA Palette Snoop

: Disabled

F5

: Old Values (Shift)F2 : Color

OS Select for DRAM >64MB

: Non-OS2

F6

: Load BIOS Defaults

 

 

F7

: Load Setup Defaults

2.Use the arrow keys to move between items and to select values. Modify the selected fields using the PgUp/PgDn/+/Ð keys. <F> keys are explained below:

<F1>:

ÒHelpÓ gives options available for each item.

Shift <F2>:

Change color.

<F5>:

Get the old values. These values are the values with

 

which the user started the current session.

<F6>:

Load all options with the BIOS Setup default values.

<F7>:

Load all options with the Power-On default values.

A short description of screen items follows:

CPU Internal

This option enables/disables the CPUÕs internal

Cache

cache. (The Default setting is Enabled.)

External Cache This option enables/disables the external cache

 

memory. (The Default setting is Enabled.)

Quick Power

Enabled provides a fast POST at boot-up .

On Self Test

 

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Contents TX P54C/P55C PCI Mainboard User’s Guide Technical Reference 5XA5Soyotm Table of Contents Page Introduction Unpacking the Mainboard Electrostatic Discharge PrecautionsTAG Sram Mainboard Layout w/ Default SettingsMainboard Default Setting Jumpers JP5 Cmos Clear JumperJP40 CE Test Jumper Pin JP37 Dimm Voltage Select Jumper JP2 Smart Detect CPU Voltage Function Auto/Manual JumperFrequency Setting CPU Type ConfigurationHardware Setup Ð1Ð3. CPU Jumper Settings P54C/P55C- 180/60 MHz Socket AMD K6 PR266 CPU Setting 4.0 x clock Single Voltage CPU Setting CPU Single/Dual Voltage SettingDual Voltage CPU Setting Memory ConfigurationCache Size and RAM Locations Cache ConfigurationMemory Configuration Table RAM Bank Installation NoticeMulti I/O Port Addresses JP43 CPU Cooling Fan Connector FDC FDC ConnectorATX PW ATX Power Supply Connectors IR1 IR Connector Reset Hardware Reset ControlHDD LED HDD LED Connector IDE1/IDE2 On-board Primary/Secondary IDE HDD ConnectorsUSB1/USB2 Universal Serial Bus Connectors PS/2 Mouse Conn. PS/2 Mouse ConnectorPRT Parallel Port Connector SPK Speaker ConnectorBios Setup Standard Cmos Setup Drive a & B Video Halt On Bios SetupCache Bios Features SetupQuick Power CPU InternalChars/Sec SettingDram 64MB PCI/VGADram Leadoff Timing Chipset Features SetupROM PCI/ISA Bios Chipset Features Setup Award SOFTWARE, INC Dram TimingSdram CAS EDO/FPPower Management Setup Memory Hole At 15M- Choose Enabled or Disabled defaultROM PCI/ISA Bios Cmos Setup Utility Power Management Setup APM Bttn IDE PNP/PCI Configuration SetupFloppy Disk Choose Enabled or Disabled Serial Port Primary/SecondaryPCI IRQ PCI IDE IRQINT# Load Bios Defaults Load Setup DefaultsIDE Secondary Slave PIO ROM PCI/ISA Bios Integrated Peripherals Award SOFTWARE, INCIntegrated Peripherals PIOUdma ECP Mode Use DMA IR Transmission DelayFIR Mode Use DMA Parallel Port ModeSupervisor Password ÒEnter PasswordÓÒConfirm PasswordÓ User Password ROM PCI/ISA Bios Cmos Setup Utility IDE HDD Auto DetectionHard Disks Appendix CPU Setting List CPU Setting List Possible CPUs Voltage SettingMemory Configuration Spread Spectrum CPU System Hardware MonitorESC