Silicon Image SSD-DXXX(I)-4210 manual Signal Descriptions, Signal Name Pins Type Description

Page 16

ELECTRICAL SPECIFICATION

 

 

SSD-DXXX(I)-4210 DATA SHEET

SIGNAL DESCRIPTIONS

 

 

 

 

Table 8: Signal Descriptions

 

 

 

 

 

 

Signal Name

Pin(s)

Type

Description

 

 

 

 

 

 

A2-A0

36, 33,

I

Address Inputs. These signals are

 

 

35

 

asserted by the host to access the task

 

 

 

 

registers in the device.

 

 

 

 

 

 

-CS0,-CS1

37, 38

I

In the true IDE mode, -CS0 is the chip

 

 

 

 

select for the task file registers while -CS1

 

 

 

 

is used to select the Alternate Status

 

 

 

 

register and the Device Control register.

 

 

 

 

 

 

-CSEL

28

I

Cable Select. This internally pulled-up

 

 

 

 

signal is used to configure this device as a

 

 

 

 

master or a slave when the jumper

 

 

 

 

configuration is in CSEL mode.

 

 

 

 

When this pin is:

 

 

 

 

• Grounded by the host, this device is

 

 

 

 

configured as a master.

 

 

 

 

• Open, this device is configured as a

 

 

 

 

slave.

 

 

 

 

 

 

D15-D0

18, 16,

I/O

Data Inputs/Outputs. This is the 8-bit or

 

 

14, 12,

 

16-bit bidirectional interface between the

 

 

10, 8, 6,

 

host and device. The lower eight bits are

 

 

4, 3, 5, 7,

 

used for 8-bit register transfers.

 

 

9, 11, 13,

 

 

 

 

15, 17

 

 

 

 

 

 

 

 

-DMACK

29

I

DMA Acknowledge. This signal is used by

 

 

 

 

the host in response to DMARQ to initiate

 

 

 

 

DMA transfers. The DMARQ/-DMACK

 

 

 

 

handshake is used to provide flow control

 

 

 

 

during the transfer. When -DMACK is

 

 

 

 

asserted, -CS0 and -CS1 are not asserted

 

 

 

 

and transfers are 16-bits wide.

 

 

 

 

 

 

DASP

39

I/O

Disk Active/Slave Present. This open

 

 

 

 

drain output signal is asserted low any time

 

 

 

 

the drive is active. In a master/slave

configuration, this signal is used by the slave to inform the master that a slave is present.

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4210D-03DSR

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FEBRUARY 2, 2009

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Contents Features OverviewUpdated Revision HistoryDocument No Release Date Changes AddedTable of Contents ATA Command Set Sales and Support Part Numbering Related DocumentationList of Figures List of Tables Idle Immediate 95h, E1h Part Numbering Nomenclature Physical Specifications Physical DimensionsPin Locations System Power Requirements Product SpecificationsSystem Performance Reliability SiliconDrive Part# Capacity Service Life GB Written per DayOperational Life Span Environmental Specifications Product Capacity SpecificationsProduct Capacity Number Sectors Bytes Cylinders Heads Track Electrical Specification Pin AssignmentsPin Ultra DMASignal Descriptions Signal Name Pins Type DescriptionData Inputs/Outputs. This is the 8-bit or Disk Active/Slave Present. This openDMA Request. This signal is used for DMA Transfers between the host and deviceThis signal is a DMA request that is used Ground. The device ground signalInterrupt Request. This signal is an active For DMA data transfers between the hostChannel Ready. The signal is negated When Udma mode DMA write is activeWhen Udma mode DMA read is active Device I/O Read. This is the read strobeSymbol Parameter Minimum Maximum Units Device Power Supply. The device powerAbsolute Maximum Ratings DC Characteristics Symbol Parameter 5V ± 10% Units Minimum MaximumTrue IDE PIO Mode Read/Write Access Timing True IDE PIO Mode Read/Write Access Timing DiagramTrue IDE PIO Mode Read/Write Access Timing True IDE Multiword DMA Read/Write Access Timing True IDE Multiword DMA Read/Write Access Timing Symbol Mode 0 Mode Mode 3 Mode 4 Note UnitsUltra DMA Data Burst Timing Requirements Initiating a Udma Data-In BurstSustained Udma Data-In Burst Device Terminating a Udma Data-In Burst Host Terminating a Udma Data-In Burst Initiating a Udma Data-Out Burst Device Pausing a Udma Data-Out Burst Host Terminating a Udma Data-Out Burst Device Terminating a Udma Data-Out Burst Udma Data Burst Timing RequirementsMin Max Min. Max Time from Strobe edge to ns ATA and True IDE Register Decoding Task File Register SpecificationCS0# CS1# DA02 DA01 DA00 Error Register ATA RegistersFeature Register OperationRead/Write ByteRead/Write Sector Count Default Value Sector Count RegisterRead/Write Sector Number RegisterLogical Block Number bits A07-A00 LBA Addressing Low Cylinder Low RegisterLogical Block Number bits A15-A08 LBA Addressing Cylinder High Register Logical Block Number bits A23-A16 LBA AddressingDrive/Head Register LBA27 LBA26 LBA25 LBA24Status Register Drive Write Fault DWF. Always set toCorrected Data CORR. Always set to Command Register Operation Read/Write ATA Command CodeAlternate Status Register Write Device Control RegisterNIEN Read/Write NWTG NHS3 NHS2 NHS1 NHS0 NDS1 NDS0 Default Value Device Address RegisterATA Command Block and SET Description ATA Command Block and Set DescriptionATA Command Set Class Command Name Registers Used CodeATA Command Set Check Power Mode 98h, E5h Check Power Mode 98h, E5hRegister Executive Drive Diagnostic 90h Executive Drive Diagnostic 90hFormat Track 50h Drive Head Number LBA27-24 Command 50hFormat Track 50h Identify Drive ECh Identify Drive EChWord Data Default Bytes Data Description Address Identify Drive Drive Attribute DataIdentify Drive Drive Attribute Data Identify Drive Drive Attribute Data Idle 97h, E3h Idle 97h, E3hIdle Immediate 95h, E1h Idle Immediate 95h, E1hInitialize Drive Parameters 91h Initialize Drive Parameters 91hRecalibrate 1Xh Drive Command 1XhRecalibrate 1Xh Read Buffer E4h Read Buffer E4hRead DMA C8h Drive Head Number LBA27-24 Command C8hRead DMA C8h Read Multiple C4h Drive Head Number LBA27-24 Command C4hRead Multiple C4h Read Sector 20h, 21h Drive Head Number LBA27-24 Command 20h or 21hRead Sector 20h, 21h Read Long Sectors 22h, 23h Drive Head Number LBA27-24 Command 22h or 23hRead Long Sectors 22h, 23h Read Verify Sectors 40h, 41h Drive Head Number LBA27-24 Command 40h or 41hRead Verify Sectors 40h, 41h Seek 7Xh Drive Head Number LBA27-24 Command 7XhSeek 7Xh Set Features EFh Set Features EFhSet Features’ Attributes Feature OperationSet Multiple Mode C6h Set Multiple Mode C6hSet Sleep Mode 99h, E6h Set Sleep Mode 99h, E6hStandby 96h, E2h Standby 96h, E2hStandby Immediate 94h, E0h Standby Immediate 94h, E0hWrite Buffer E8h Write Buffer E8hWrite DMA CAh Drive Head NumberLBA27-24 Command CAhWrite DMA CAh Write Multiple C5h Drive Head NumberLBA27-24 Command C5hWrite Multiple C5h Write Sectors 30h, 31h Drive Head Number LBA27-24 Command 30h or 31hWrite Sectors 30h, 31h Write Long Sectors 32h, 33h Drive Head Number LBA27-24 Command 32h or 33hWrite Long Sectors 32h, 33h Erase Sectors C0h Drive Head Number LBA27-24 Command C0hErase Sectors C0h Extended Error Codes Extended Error Codes DescriptionRequest Sense 03h Request Sense 03hTranslate Sector 87h Drive Head Number LBA27-24 Command 87hTranslate Sector 87h Wear-Level F5h Wear-Level F5hWrite Multiple w/o Erase CDh Drive Head Number LBA27-24 Command CDhWrite Multiple w/o Erase CDh Write Sectors w/o Erase 38h Drive Head Number LBA27-24 Command 38hWrite Sectors w/o Erase 38h Write Verify 3Ch Drive Head Number LBA27-24 Command 3ChWrite Verify 3Ch Sales and Support Part NumberingPart Numbering Nomenclature Part NumbersStandard Back Label with Front Label Lot Code InformationRelated Documentation Related DocumentationSiliconDrive EP Application-Specific Description Technology

SSD-DXXX(I)-4210 specifications

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