Silicon Image SSD-DXXX(I)-4210 manual Device Control Register, Write, Nien

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ATA REGISTERS

SSD-DXXX(I)-4210 DATA SHEET

DEVICE CONTROL REGISTER

The Device Control register is used to control the interrupt request and issue ATA software resets.

Table 25: Device Control Register

Operation

D7

D6

D5

D4

D3

D2

D1

D0

Write

-

-

-

-

1

SRST

nIEN

0

 

 

 

 

 

 

 

 

 

Bit(s) Description

7-4 Reserved bits.

3 Always set to 1.

2 Software Reset (SRST). When set, resets the ATA software.

1Interrupt Enable (nIEN). When set, device interrupts are disabled. There is no function in the memory-mapped mode.

0 Always set to 0.

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4210D-03DSR

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FEBRUARY 2, 2009

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Contents Overview FeaturesAdded UpdatedRevision History Document No Release Date ChangesTable of Contents ATA Command Set Related Documentation Sales and Support Part NumberingList of Figures List of Tables Idle Immediate 95h, E1h Part Numbering Nomenclature Physical Dimensions Physical SpecificationsPin Locations System Performance Product SpecificationsSystem Power Requirements Operational Life Span SiliconDrive Part# Capacity Service Life GB Written per DayReliability Product Capacity Number Sectors Bytes Cylinders Heads Track Product Capacity SpecificationsEnvironmental Specifications Ultra DMA Electrical SpecificationPin Assignments PinDisk Active/Slave Present. This open Signal DescriptionsSignal Name Pins Type Description Data Inputs/Outputs. This is the 8-bit orTransfers between the host and device DMA Request. This signal is used for DMAFor DMA data transfers between the host This signal is a DMA request that is usedGround. The device ground signal Interrupt Request. This signal is an activeDevice I/O Read. This is the read strobe Channel Ready. The signal is negatedWhen Udma mode DMA write is active When Udma mode DMA read is activeAbsolute Maximum Ratings Device Power Supply. The device powerSymbol Parameter Minimum Maximum Units Symbol Parameter 5V ± 10% Units Minimum Maximum DC CharacteristicsTrue IDE PIO Mode Read/Write Access Timing Diagram True IDE PIO Mode Read/Write Access TimingTrue IDE PIO Mode Read/Write Access Timing True IDE Multiword DMA Read/Write Access Timing Symbol Mode 0 Mode Mode 3 Mode 4 Note Units True IDE Multiword DMA Read/Write Access TimingInitiating a Udma Data-In Burst Ultra DMA Data Burst Timing RequirementsSustained Udma Data-In Burst Device Terminating a Udma Data-In Burst Host Terminating a Udma Data-In Burst Initiating a Udma Data-Out Burst Device Pausing a Udma Data-Out Burst Host Terminating a Udma Data-Out Burst Udma Data Burst Timing Requirements Device Terminating a Udma Data-Out BurstMin Max Min. Max Time from Strobe edge to ns CS0# CS1# DA02 DA01 DA00 Task File Register SpecificationATA and True IDE Register Decoding ATA Registers Error RegisterByte Feature RegisterOperation Read/WriteSector Count Register Read/Write Sector Count Default ValueLogical Block Number bits A07-A00 LBA Addressing Sector Number RegisterRead/Write Logical Block Number bits A15-A08 LBA Addressing Cylinder Low RegisterLow Logical Block Number bits A23-A16 LBA Addressing Cylinder High RegisterLBA27 LBA26 LBA25 LBA24 Drive/Head RegisterCorrected Data CORR. Always set to Drive Write Fault DWF. Always set toStatus Register Operation Read/Write ATA Command Code Command RegisterAlternate Status Register NIEN Device Control RegisterWrite Device Address Register Read/Write NWTG NHS3 NHS2 NHS1 NHS0 NDS1 NDS0 Default ValueClass Command Name Registers Used Code ATA Command Block and SET DescriptionATA Command Block and Set Description ATA Command SetATA Command Set Register Check Power Mode 98h, E5hCheck Power Mode 98h, E5h Executive Drive Diagnostic 90h Executive Drive Diagnostic 90hFormat Track 50h Drive Head Number LBA27-24 Command 50hFormat Track 50h Identify Drive ECh Identify Drive EChIdentify Drive Drive Attribute Data Word Data Default Bytes Data Description AddressIdentify Drive Drive Attribute Data Identify Drive Drive Attribute Data Idle 97h, E3h Idle 97h, E3hIdle Immediate 95h, E1h Idle Immediate 95h, E1hInitialize Drive Parameters 91h Initialize Drive Parameters 91hRecalibrate 1Xh Drive Command 1XhRecalibrate 1Xh Read Buffer E4h Read Buffer E4hRead DMA C8h Drive Head Number LBA27-24 Command C8hRead DMA C8h Read Multiple C4h Drive Head Number LBA27-24 Command C4hRead Multiple C4h Read Sector 20h, 21h Drive Head Number LBA27-24 Command 20h or 21hRead Sector 20h, 21h Read Long Sectors 22h, 23h Drive Head Number LBA27-24 Command 22h or 23hRead Long Sectors 22h, 23h Read Verify Sectors 40h, 41h Drive Head Number LBA27-24 Command 40h or 41hRead Verify Sectors 40h, 41h Seek 7Xh Drive Head Number LBA27-24 Command 7XhSeek 7Xh Feature Operation Set Features EFhSet Features EFh Set Features’ AttributesSet Multiple Mode C6h Set Multiple Mode C6hSet Sleep Mode 99h, E6h Set Sleep Mode 99h, E6hStandby 96h, E2h Standby 96h, E2hStandby Immediate 94h, E0h Standby Immediate 94h, E0hWrite Buffer E8h Write Buffer E8hWrite DMA CAh Drive Head NumberLBA27-24 Command CAhWrite DMA CAh Write Multiple C5h Drive Head NumberLBA27-24 Command C5hWrite Multiple C5h Write Sectors 30h, 31h Drive Head Number LBA27-24 Command 30h or 31hWrite Sectors 30h, 31h Write Long Sectors 32h, 33h Drive Head Number LBA27-24 Command 32h or 33hWrite Long Sectors 32h, 33h Erase Sectors C0h Drive Head Number LBA27-24 Command C0hErase Sectors C0h Request Sense 03h Extended Error CodesExtended Error Codes Description Request Sense 03hTranslate Sector 87h Drive Head Number LBA27-24 Command 87hTranslate Sector 87h Wear-Level F5h Wear-Level F5hWrite Multiple w/o Erase CDh Drive Head Number LBA27-24 Command CDhWrite Multiple w/o Erase CDh Write Sectors w/o Erase 38h Drive Head Number LBA27-24 Command 38hWrite Sectors w/o Erase 38h Write Verify 3Ch Drive Head Number LBA27-24 Command 3ChWrite Verify 3Ch Part Numbers Sales and SupportPart Numbering Part Numbering NomenclatureFront Label Lot Code Information Standard Back Label withTechnology Related DocumentationRelated Documentation SiliconDrive EP Application-Specific Description

SSD-DXXX(I)-4210 specifications

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