Silicon Image SSD-DXXX(I)-4210 manual Device Terminating a Udma Data-Out Burst

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ELECTRICAL SPECIFICATION

SSD-DXXX(I)-4210 DATA SHEET

DMARQ (device)

DMACK-

(host)

tLI tMLI

STOP (host)

tRP

DDMARDY-

(device)

tRFS

tLI

 

 

 

tMLI

 

 

HSTROBE

(host)

tDVS

DD(15:0)

tACK

tIORDYZ

tACK

tDVH

(host)

CRC

tACK

DA0, DA1, DA2,

CS0-, CS1-

Figure 15: Device Terminating a UDMA Data-Out Burst

Note: The definitions for the DIOW-:STOP, IORDY:DDMARDY- :DSTROBE, and DIOR-:HDMARDY-:HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Table 13: UDMA Data Burst Timing Requirements

Symbol

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Comment (see Notes 1 and

Units

 

 

 

 

 

 

 

 

 

 

Min. Max.

Min. Max.

Min. Max.

Min. Max.

Min. Max.

2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t2CYCTYP

240

-

160

-

120

-

90

-

60

-

Typical sustained average

ns

 

 

 

 

 

 

 

 

 

 

 

two-cycle time.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

112

-

73

-

54

-

39

-

25

-

Cycle time allowing for

ns

 

 

 

 

 

 

 

 

 

 

 

asymmetry and clock

 

 

 

 

 

 

 

 

 

 

 

 

variations (from STROBE

 

 

 

 

 

 

 

 

 

 

 

 

edge to STROBE edge).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t2CYC

230

-

154

-

115

-

86

-

57

-

Two-cycle time allowing for

ns

 

 

 

 

 

 

 

 

 

 

 

clock variations (from rising

 

 

 

 

 

 

 

 

 

 

 

 

edge to next rising edge, or

 

 

 

 

 

 

 

 

 

 

 

 

from falling edge to next

 

 

 

 

 

 

 

 

 

 

 

 

falling edge of STROBE).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDS

15

 

10

 

7

 

7

 

5

 

Data setup time at recipient.

ns

tDH

5

-

5

-

5

-

5

-

5

-

Data hold time at recipient.

ns

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4210D-03DSR

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FEBRUARY 2, 2009

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Contents Overview FeaturesRevision History UpdatedDocument No Release Date Changes AddedTable of Contents ATA Command Set Related Documentation Sales and Support Part NumberingList of Figures List of Tables Idle Immediate 95h, E1h Part Numbering Nomenclature Physical Dimensions Physical SpecificationsPin Locations Product Specifications System Power RequirementsSystem Performance SiliconDrive Part# Capacity Service Life GB Written per Day ReliabilityOperational Life Span Product Capacity Specifications Environmental SpecificationsProduct Capacity Number Sectors Bytes Cylinders Heads Track Pin Assignments Electrical SpecificationPin Ultra DMASignal Name Pins Type Description Signal DescriptionsData Inputs/Outputs. This is the 8-bit or Disk Active/Slave Present. This openTransfers between the host and device DMA Request. This signal is used for DMAGround. The device ground signal This signal is a DMA request that is usedInterrupt Request. This signal is an active For DMA data transfers between the hostWhen Udma mode DMA write is active Channel Ready. The signal is negatedWhen Udma mode DMA read is active Device I/O Read. This is the read strobeDevice Power Supply. The device power Symbol Parameter Minimum Maximum UnitsAbsolute Maximum Ratings Symbol Parameter 5V ± 10% Units Minimum Maximum DC CharacteristicsTrue IDE PIO Mode Read/Write Access Timing Diagram True IDE PIO Mode Read/Write Access TimingTrue IDE PIO Mode Read/Write Access Timing True IDE Multiword DMA Read/Write Access Timing Symbol Mode 0 Mode Mode 3 Mode 4 Note Units True IDE Multiword DMA Read/Write Access TimingInitiating a Udma Data-In Burst Ultra DMA Data Burst Timing RequirementsSustained Udma Data-In Burst Device Terminating a Udma Data-In Burst Host Terminating a Udma Data-In Burst Initiating a Udma Data-Out Burst Device Pausing a Udma Data-Out Burst Host Terminating a Udma Data-Out Burst Udma Data Burst Timing Requirements Device Terminating a Udma Data-Out BurstMin Max Min. Max Time from Strobe edge to ns Task File Register Specification ATA and True IDE Register DecodingCS0# CS1# DA02 DA01 DA00 ATA Registers Error RegisterOperation Feature RegisterRead/Write ByteSector Count Register Read/Write Sector Count Default ValueSector Number Register Read/WriteLogical Block Number bits A07-A00 LBA Addressing Cylinder Low Register LowLogical Block Number bits A15-A08 LBA Addressing Logical Block Number bits A23-A16 LBA Addressing Cylinder High RegisterLBA27 LBA26 LBA25 LBA24 Drive/Head RegisterDrive Write Fault DWF. Always set to Status RegisterCorrected Data CORR. Always set to Operation Read/Write ATA Command Code Command RegisterAlternate Status Register Device Control Register WriteNIEN Device Address Register Read/Write NWTG NHS3 NHS2 NHS1 NHS0 NDS1 NDS0 Default ValueATA Command Block and Set Description ATA Command Block and SET DescriptionATA Command Set Class Command Name Registers Used CodeATA Command Set Check Power Mode 98h, E5h Check Power Mode 98h, E5hRegister Executive Drive Diagnostic 90h Executive Drive Diagnostic 90hDrive Head Number LBA27-24 Command 50h Format Track 50hFormat Track 50h Identify Drive ECh Identify Drive EChIdentify Drive Drive Attribute Data Word Data Default Bytes Data Description AddressIdentify Drive Drive Attribute Data Identify Drive Drive Attribute Data Idle 97h, E3h Idle 97h, E3hIdle Immediate 95h, E1h Idle Immediate 95h, E1hInitialize Drive Parameters 91h Initialize Drive Parameters 91hDrive Command 1Xh Recalibrate 1XhRecalibrate 1Xh Read Buffer E4h Read Buffer E4hDrive Head Number LBA27-24 Command C8h Read DMA C8hRead DMA C8h Drive Head Number LBA27-24 Command C4h Read Multiple C4hRead Multiple C4h Drive Head Number LBA27-24 Command 20h or 21h Read Sector 20h, 21hRead Sector 20h, 21h Drive Head Number LBA27-24 Command 22h or 23h Read Long Sectors 22h, 23hRead Long Sectors 22h, 23h Drive Head Number LBA27-24 Command 40h or 41h Read Verify Sectors 40h, 41hRead Verify Sectors 40h, 41h Drive Head Number LBA27-24 Command 7Xh Seek 7XhSeek 7Xh Set Features EFh Set Features EFhSet Features’ Attributes Feature OperationSet Multiple Mode C6h Set Multiple Mode C6hSet Sleep Mode 99h, E6h Set Sleep Mode 99h, E6hStandby 96h, E2h Standby 96h, E2hStandby Immediate 94h, E0h Standby Immediate 94h, E0hWrite Buffer E8h Write Buffer E8hDrive Head NumberLBA27-24 Command CAh Write DMA CAhWrite DMA CAh Drive Head NumberLBA27-24 Command C5h Write Multiple C5hWrite Multiple C5h Drive Head Number LBA27-24 Command 30h or 31h Write Sectors 30h, 31hWrite Sectors 30h, 31h Drive Head Number LBA27-24 Command 32h or 33h Write Long Sectors 32h, 33hWrite Long Sectors 32h, 33h Drive Head Number LBA27-24 Command C0h Erase Sectors C0hErase Sectors C0h Extended Error Codes Description Extended Error CodesRequest Sense 03h Request Sense 03hDrive Head Number LBA27-24 Command 87h Translate Sector 87hTranslate Sector 87h Wear-Level F5h Wear-Level F5hDrive Head Number LBA27-24 Command CDh Write Multiple w/o Erase CDhWrite Multiple w/o Erase CDh Drive Head Number LBA27-24 Command 38h Write Sectors w/o Erase 38hWrite Sectors w/o Erase 38h Drive Head Number LBA27-24 Command 3Ch Write Verify 3ChWrite Verify 3Ch Part Numbering Sales and SupportPart Numbering Nomenclature Part NumbersFront Label Lot Code Information Standard Back Label withRelated Documentation Related DocumentationSiliconDrive EP Application-Specific Description Technology

SSD-DXXX(I)-4210 specifications

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