Silicon Image SSD-DXXX(I)-4210 manual Channel Ready. The signal is negated

Page 19

ELECTRICAL SPECIFICATION

 

 

SSD-DXXX(I)-4210 DATA SHEET

 

 

Table 8:

Signal Descriptions (Continued)

 

 

 

 

 

 

Signal Name

Pin(s)

Type

Description

 

 

 

 

 

 

IORDY

27

I

I/O Channel Ready. The signal is negated

 

(True IDE

 

 

to extend the host transfer cycle of any host

 

mode)

 

 

register access.

 

 

 

 

 

 

-IORD

25

I

Device I/O Read. This is the read strobe

 

(True IDE

 

 

signal from the host. The falling edge of

 

mode)

 

 

IORD enables data from the device onto

 

 

 

 

the data bus. The rising edge of IORD

 

 

 

 

latches data at the host. The host does not

 

 

 

 

act on the data until it is latched.

 

 

 

 

 

 

-DDMARDY

 

 

When UDMA mode DMA write is active in

 

(UDMA write

 

 

all modes, this signal is asserted by the

 

protocol

 

 

device during a data burst to indicate that

 

active)

 

 

the device is ready to receive UDMA data-

 

 

 

 

out bursts.

 

 

 

 

The device may negate -DDMARDY to

 

 

 

 

pause a UDMA transfer.

 

 

 

 

 

 

DSTROBE

 

 

When UDMA mode DMA read is active in

 

(UDMA read

 

 

all modes, this signal is the data in strobe

 

protocol

 

 

generated by the device. Both the rising

 

active)

 

 

and falling edge of DSTROBE cause data

 

 

 

 

to be latched by the host. The device may

 

 

 

 

stop generating DSTROBE edges to pause

 

 

 

 

a UDMA data-in burst.

 

 

 

 

 

 

-IOWR

23

I

Device I/O Write. This is the write strobe

 

(True IDE

 

 

signal from the host. The rising edge of

 

mode)

 

 

IOWR# latches data from the data bit

 

 

 

 

signals. The device does not act on the

data until it is latched.

-HDMARDY

(UDMA read protocol active)

When UDMA mode DMA read is active in all modes, this signal is asserted by the host to indicate that the host is ready to receive UDMA data-in bursts. The host may negate -HDMARDY to pause a UDMA transfer.

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4210D-03DSR

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FEBRUARY 2, 2009

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Contents Overview FeaturesAdded UpdatedRevision History Document No Release Date ChangesTable of Contents ATA Command Set Related Documentation Sales and Support Part NumberingList of Figures List of Tables Idle Immediate 95h, E1h Part Numbering Nomenclature Physical Dimensions Physical SpecificationsPin Locations System Power Requirements Product SpecificationsSystem Performance Reliability SiliconDrive Part# Capacity Service Life GB Written per DayOperational Life Span Environmental Specifications Product Capacity SpecificationsProduct Capacity Number Sectors Bytes Cylinders Heads Track Ultra DMA Electrical SpecificationPin Assignments PinDisk Active/Slave Present. This open Signal DescriptionsSignal Name Pins Type Description Data Inputs/Outputs. This is the 8-bit orTransfers between the host and device DMA Request. This signal is used for DMAFor DMA data transfers between the host This signal is a DMA request that is usedGround. The device ground signal Interrupt Request. This signal is an activeDevice I/O Read. This is the read strobe Channel Ready. The signal is negatedWhen Udma mode DMA write is active When Udma mode DMA read is activeSymbol Parameter Minimum Maximum Units Device Power Supply. The device powerAbsolute Maximum Ratings Symbol Parameter 5V ± 10% Units Minimum Maximum DC CharacteristicsTrue IDE PIO Mode Read/Write Access Timing Diagram True IDE PIO Mode Read/Write Access TimingTrue IDE PIO Mode Read/Write Access Timing True IDE Multiword DMA Read/Write Access Timing Symbol Mode 0 Mode Mode 3 Mode 4 Note Units True IDE Multiword DMA Read/Write Access TimingInitiating a Udma Data-In Burst Ultra DMA Data Burst Timing RequirementsSustained Udma Data-In Burst Device Terminating a Udma Data-In Burst Host Terminating a Udma Data-In Burst Initiating a Udma Data-Out Burst Device Pausing a Udma Data-Out Burst Host Terminating a Udma Data-Out Burst Udma Data Burst Timing Requirements Device Terminating a Udma Data-Out BurstMin Max Min. Max Time from Strobe edge to ns ATA and True IDE Register Decoding Task File Register SpecificationCS0# CS1# DA02 DA01 DA00 ATA Registers Error RegisterByte Feature RegisterOperation Read/WriteSector Count Register Read/Write Sector Count Default ValueRead/Write Sector Number RegisterLogical Block Number bits A07-A00 LBA Addressing Low Cylinder Low RegisterLogical Block Number bits A15-A08 LBA Addressing Logical Block Number bits A23-A16 LBA Addressing Cylinder High RegisterLBA27 LBA26 LBA25 LBA24 Drive/Head RegisterStatus Register Drive Write Fault DWF. Always set toCorrected Data CORR. Always set to Operation Read/Write ATA Command Code Command RegisterAlternate Status Register Write Device Control RegisterNIEN Device Address Register Read/Write NWTG NHS3 NHS2 NHS1 NHS0 NDS1 NDS0 Default ValueClass Command Name Registers Used Code ATA Command Block and SET DescriptionATA Command Block and Set Description ATA Command SetATA Command Set Check Power Mode 98h, E5h Check Power Mode 98h, E5hRegister Executive Drive Diagnostic 90h Executive Drive Diagnostic 90hFormat Track 50h Drive Head Number LBA27-24 Command 50hFormat Track 50h Identify Drive ECh Identify Drive EChIdentify Drive Drive Attribute Data Word Data Default Bytes Data Description AddressIdentify Drive Drive Attribute Data Identify Drive Drive Attribute Data Idle 97h, E3h Idle 97h, E3hIdle Immediate 95h, E1h Idle Immediate 95h, E1hInitialize Drive Parameters 91h Initialize Drive Parameters 91hRecalibrate 1Xh Drive Command 1XhRecalibrate 1Xh Read Buffer E4h Read Buffer E4hRead DMA C8h Drive Head Number LBA27-24 Command C8hRead DMA C8h Read Multiple C4h Drive Head Number LBA27-24 Command C4hRead Multiple C4h Read Sector 20h, 21h Drive Head Number LBA27-24 Command 20h or 21hRead Sector 20h, 21h Read Long Sectors 22h, 23h Drive Head Number LBA27-24 Command 22h or 23hRead Long Sectors 22h, 23h Read Verify Sectors 40h, 41h Drive Head Number LBA27-24 Command 40h or 41hRead Verify Sectors 40h, 41h Seek 7Xh Drive Head Number LBA27-24 Command 7XhSeek 7Xh Feature Operation Set Features EFhSet Features EFh Set Features’ AttributesSet Multiple Mode C6h Set Multiple Mode C6hSet Sleep Mode 99h, E6h Set Sleep Mode 99h, E6hStandby 96h, E2h Standby 96h, E2hStandby Immediate 94h, E0h Standby Immediate 94h, E0hWrite Buffer E8h Write Buffer E8hWrite DMA CAh Drive Head NumberLBA27-24 Command CAhWrite DMA CAh Write Multiple C5h Drive Head NumberLBA27-24 Command C5hWrite Multiple C5h Write Sectors 30h, 31h Drive Head Number LBA27-24 Command 30h or 31hWrite Sectors 30h, 31h Write Long Sectors 32h, 33h Drive Head Number LBA27-24 Command 32h or 33hWrite Long Sectors 32h, 33h Erase Sectors C0h Drive Head Number LBA27-24 Command C0hErase Sectors C0h Request Sense 03h Extended Error CodesExtended Error Codes Description Request Sense 03hTranslate Sector 87h Drive Head Number LBA27-24 Command 87hTranslate Sector 87h Wear-Level F5h Wear-Level F5hWrite Multiple w/o Erase CDh Drive Head Number LBA27-24 Command CDhWrite Multiple w/o Erase CDh Write Sectors w/o Erase 38h Drive Head Number LBA27-24 Command 38hWrite Sectors w/o Erase 38h Write Verify 3Ch Drive Head Number LBA27-24 Command 3ChWrite Verify 3Ch Part Numbers Sales and SupportPart Numbering Part Numbering NomenclatureFront Label Lot Code Information Standard Back Label withTechnology Related DocumentationRelated Documentation SiliconDrive EP Application-Specific Description

SSD-DXXX(I)-4210 specifications

The Silicon Image SSD-DXXX(I)-4210 is a cutting-edge solid-state drive designed for high-performance computing applications. Designed to cater to both consumer and enterprise markets, the SSD-DXXX(I)-4210 stands out for its robust features and advanced technologies, making it an ideal choice for those who demand reliability and speed.

One of the key features of the SSD-DXXX(I)-4210 is its exceptional read and write speeds. With read speeds reaching up to 550 MB/s and write speeds up to 520 MB/s, the drive significantly reduces loading times for applications and files. This performance is enhanced by the integrated SMI controller, which optimizes data transfer and minimizes latency, ensuring seamless multitasking and efficient workflows.

Another noteworthy aspect of the Silicon Image SSD-DXXX(I)-4210 is its endurance and lifespan. Thanks to advanced wear leveling algorithms and error correction technologies, this SSD maintains data integrity even in demanding environments. With an endurance rating of up to 200 terabytes written (TBW), users can rely on the SSD for longevity, making it suitable for intensive applications such as video editing and large database management.

The SSD-DXXX(I)-4210 is built using 3D NAND flash memory, which not only increases storage density but also provides better performance and reliability compared to traditional 2D NAND. This technology allows for higher capacity options while reducing power consumption, resulting in energy-efficient operation. Users can select from multiple storage capacities, catering to various needs, from casual users to data-intensive enterprises.

In terms of connectivity, the SSD supports both SATA III and NVMe interfaces, giving users the flexibility to integrate it into a variety of systems. The SSD-DXXX(I)-4210 is also backwards compatible with older SATA specifications, ensuring broad compatibility across different devices.

Additionally, the SSD-DXXX(I)-4210 comes with built-in thermal throttling technology that protects the drive from overheating during heavy usage. This feature enhances the overall reliability and performance of the drive, making it a safe option for high-demand applications.

In summary, the Silicon Image SSD-DXXX(I)-4210 combines top-tier performance with advanced technologies and reliable features, making it an excellent solution for users looking to enhance their computing experience. With its fast speeds, longevity, and versatile connectivity options, this SSD represents a smart investment for anyone looking to upgrade their storage capabilities.
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