ATA COMMAND BLOCK AND SET DESCRIPTION |
ATA COMMAND BLOCK AND SET DESCRIPTION
In accordance with the ANSI ATA Specification, the device implements seven registers that are used to transfer instructions to the device by the host. These commands follow the ANSI standard ATA protocol. A description of the ATA command block is provided in the following table.
Table 29: ATA Command Block and Set Description
| Operation |
| D7 |
| D6 |
| D5 |
| D4 |
| D3 | D2 |
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| D1 | D0 | ||
| Feature |
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| X |
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| Sector Count |
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| X |
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| Sector Number |
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| X |
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| Cylinder Low |
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| X |
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| Cylinder High |
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| X |
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| Drive Head |
| 1 |
| LBA |
| 1 |
| Drive |
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| X |
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| Command |
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| X |
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ATA COMMAND SET |
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| Table 30: ATA Command Set |
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| Class | Command Name | Command |
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| Registers Used |
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| Code |
| FR |
| SC | SN | CY | DH | LBA | |||||||||
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| 1 | Check Power Mode | 98h, E5h |
| - | - | - | - |
| D | - | |||||||
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1 | Execute Drive |
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| 90h |
| - | - | - | - |
| D | - | ||||||
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| Diagnostics |
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1 | Erase Sector |
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| C0h |
| - |
| Y | Y | Y | Y | Y | ||||||
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2 | Format Track |
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| 50h |
| - |
| Y | - | Y | Y | Y | ||||||
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1 | Identify Drive |
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| ECh |
| - | - | - | - |
| D | - | ||||||
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1 | Idle |
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| 97h, E3h |
| - |
| Y | - | - |
| D | - | ||||
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1 | Idle Immediate |
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| 95h, E1h |
| - |
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| D | - | |||||
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1 | Initialize Drive |
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| 91h |
| - |
| Y | - | - |
| Y | - | |||||
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| Parameters |
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1 | Read Buffer |
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| E4h |
| - | - | - | - |
| D | - | |||||
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1 | Read DMA* |
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| C8h |
| - |
| Y | Y | Y | Y | Y | |||||
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1 | Read Multiple |
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| C4h |
| - |
| Y | Y | Y | Y | Y | ||||||
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SILICONSYSTEMS PROPRIETARY
This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.
All unauthorized use and/or reproduction is prohibited.
DOCUMENT: | JUNE 17, 2008 | PAGE 27 |