Siemens S7-300 appendix Evaluation of measured values

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Memory concept

4.2 Memory functions

The data written to load memory are portable and retentive on CPU memory reset.

Evaluation of measured values:

Measured value DBs saved to load memory can be uploaded and evaluated by other communication partners (PG, PC, for example).

Note

The active system functions SFC 82 to 84 (current access to the MMC) have a distinct influence on PG functions (block status, variable status, load block, upload, open, for example). This typically reduces performance (compared to passive system functions) by the factor 10.

Note

For CPUs with firmware V2.1.0 or higher, you can also generate non-retentive DBs using SFC 82 (parameter ATTRIB -> NON_RETAIN bit.)

Note

As a precaution against loss of data, always make sure that you do not exceed the maximum number of delete/write operations. For further information, refer to the Technical Data of the Micro Memory Card (MMC) in the General Technical Data of your CPU.

Caution

Data on a SIMATIC Micro Memory Card can be corrupted if you remove the card while it is being accessed by a write operation. In this case, you may have to delete the MMC on your PG, or format the card in the CPU. Never remove an MMC in RUN mode. Always remove it when power is off, or when the CPU is in STOP state, and when the PG is not a writing to the card. When the CPU is in STOP mode and you cannot not determine whether or not a PG is writing to the card (e.g. load/delete block), disconnect the communication lines.

4-18

CPU 31xC and CPU 31x, Technical data

Manual, Edition 08/2004, A5E00105475-05

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Contents Preface ManualEdition 08/2004 Safety Guidelines Purpose of the Manual Required basic knowledgeArea of application IiiApprovals CE labelTick mark StandardsDocumentation classification This manual is part of the S7-300 documentation packageRecycling and Disposal Additional information requiredTable of contents Table of contents Index-1 Tables Retentivity of the RAM Table A-1 XiiInformation on Is available Selecting and configuringOverview Guide to the S7-300 documentation CPU performance Programming Manual From Profibus DP to Profinet X11 X12 Operating and display elements CPU 31xCOperating and display elements of CPU 31xC Slot for the Simatic Micro Memory Card MMC Integrated I/Os of CPU 31xC CPU 314C-2 PtP, for exampleMode selector switch Power supply connectionReference Differences between the CPUsStatus and Error Indicators CPU 31xC LED designation Color MeaningOperating and display elements Operating and display elements CPUOperating and display elements CPU 312, 314, 315-2 DP Mode selector switch is used to set the CPU operating mode Operating and display elements CPU 317-2 DP Use the mode selector switch to set the CPU operating mode Operating and display elements CPU 31x-2 PN/DP Slot for the Simatic Micro Memory Card MMC Displays for the X1 and X2 interfaces Status and error displays of the CPUGeneral status and error displays CPU 31xC and CPU 31x, Technical data Interfaces Multi-Point Interface MPIAvailability PropertiesDevices capable of MPI communication Operating modes for CPUs with two DP interfacesS7-300 / S7-400 with MPI interface S7-200 19.2 kbps only MPI/DP interface Profibus DP interfaceRequirements Connecting to Industrial EthernetDevices capable of Profibus DP communication Devices capable of Profinet PN communication Properties of Profinet interfaceSee also Profinet IO SystemPoint to Point PtP Transmission rateDrivers Devices capable of PtP communicationCommunication services Overview of communication servicesSelecting the communication service Overview of communication servicesData exchanged by means of S7 basic communication PG communicationOP communication Use in server mode for Configuration5 S7 communication Use as clientSend and receive conditions Global data communication MPI onlyReduction ratio Routing GD resources of the CPUsCPU 315-2 DP 315-2 PN/DPRouting network nodes MPI DP Routing network nodes MPI DP Ethernet Number of routed connections2 DP 317-2 PN/DPRequirements Routing Example of a TeleService application Real installationConfiguration in Step PtP communication What is PROFINET?? Data consistencyCommunication via Profinet only CPU 31x-2 PN/DP With PUT/GET functionsImplementation of Profinet by us What is Profinet CBA Component based Automation?Objectives in Profinet ,2DWD9LHZ 352,17,2 Extent of Profinet CBA and Profinet IOFurther Information Graphic displays Profinet IO System Extended Functions of Profinet IOFollowing graphic shows the new functions of Profinet IO Profinet PN Blocks in Profinet IO Chapter ContentCompatibility of the New Blocks Blocks NewDetailed Information Applicability System status lists SSLs in Profinet IO Chapter ContentCompatibility of the new SSLs How to use open IE communication Data block for the configuration of the connectionOpen communication via Industrial Ethernet Requirements FunctionalityDisconnecting Establishing a connection for communicationData exchange Communication interruptions1 S7 connection as communication path Snmp communication service AvailabilityS7 connections Reservation during configuration Assignment of S7 connectionsConnection points Transition pointAllocating connection resources to Ocms services Assigning connections in the programTime sequence for allocation of S7 connection resources ExampleDistribution of connection resources Communication service DistributionDistribution and availability of S7 connection resources Availability of connection resources Total number Reserved for Free Connection S7 connectionsS7 basic ResourcesConnection resources for routing Number of connection resources for routingExample of a CPU 314C-2 DP Example for a CPU 317-2 PN/DPRequirement for using the DPV1 functionality with DP slaves DPV1Definition DPV1 Extended functions of DPV1Interrupt blocks with DPV1 functionality System blocks with DPV1 functionalityProfibus DP FunctionalityCommunication 3.4 DPV1 Memory areas and retentivity CPU memory areasThree memory areas of your CPU Load memoryRetentivity of the load memory, system memory and RAM System memoryRAM Retentive data in load memoryRetentivity of memory objects Retentive data in RAMRetentive behavior of memory objects Retentive behavior of a DB for CPUs with firmwareRetentive behavior of a DB for CPUs with firmware = RUN-STOPAddress areas of system memory Address areas of system memoryProcess image Address areas DescriptionProcess image update TimeConfigurable process image with CPU317 FW V2.3.0 or higher Local data Retentivity of the load memory, system memory and RAMProperties of an MMC Properties of the Micro Memory Card MMCMMC as memory module for the CPU MMC copy protection Useful life of an MMCMemory functions General Memory functionsLoading user program from Micro Memory Card MMC to the CPU Memory functionsUploading blocks Handling with modulesDownload of new blocks or delta downloads CPU memory reset and restart CPU memory resetDeleting blocks Compressing blocksRestart warm start Recipes IntroductionProcessing sequence Recipe Recipe nMemory concept Memory functions Working memory Measured value log filesMeasured values Evaluation of measured values Backup of project data to a Micro Memory Card MMC Function principleMemory concept Memory functions Reference Execution time OverviewReference Cycle time Cycle time OverviewMeaning of the term cycle time Time slice modelStep Sequence Sequence of cyclic program processingTime slices 1 ms each Extending the cycle time Process image update Calculating the cycle timeExtending the user program processing time + 60 μs per rackConst Portions CPU FactorProcess Diagnostic Time-of-day Cycle control at the scan cycle check point CCPWatchdog InterruptExtension of the cycle time due to error Programming errors Access errorsDifferent cycle times Block processing times may fluctuateCommunication load Maximum cycle timeExample 20 % communication load Example 50 % communication loadTips Physical cycle time depending on communication loadInfluence on the physical cycle time Configuration during parameter assignment Cycle extension through component-based automation CBARuntimes Extending the OB1 cycle timeProfibus Tips and notes Additional marginal conditionsBase load through Profibus devices Update times for Profinet IO Response timeDefinition of response time Fluctuation widthDP cycle times in the Profibus DP network 17 msShortest response time Conditions for the shortest response timeCalculation Shortest response time is the sumDelay of inputs + DP cycle time at Profibus DP Delay of outputs + DP cycle time at Profibus DPLongest response time Conditions for the longest response timeReducing the response time with direct I/O access Reducing the response timeLongest response time is the sum Shortest response time Longest response timeCycle extension through component-based automation CBA Calculating method for calculating the cycle/response timeCycle time Response time Shortest response time Longest response timeDefinition of interrupt response time Process/diagnostic interrupt response times of the CPUsInterrupt response time Signal modules Tv 200 μs + 1000 μs x n%Reproducibility of delay interrupts and watchdog interrupts Process interrupt processingDefinition of Reproducibility ReproducibilitySample calculations Example of cycle time calculationSample of response time calculation Calculating the longest response timeCalculation of the longest response time Example of interrupt response time calculation Cycle and reaction times 5.6 Sample calculations General technical data Dimensions of CPU 31xCWidth of CPU WidthTechnical data of the Micro Memory Card MMC Plug-in Simatic Micro Memory CardsMaximum number of loadable blocks in the MMC Following memory modules are availableTechnical data CPU 312CAddress areas I/O Technical dataData areas and their retentivity Testing and commissioning functions Technical data AssemblyS7 signaling functions Communication functions Interfaces 1st interfaceTechnical data Functionality DimensionsProgramming Integrated functionsTechnical data of CPU 31xC 6.3 CPU 313C CPU 313CTechnical data Timers/counters and their retentivity Technical data Address areas I/O Technical data MPI Technical data Integrated I/O KHz see the Manual Technological FunctionsTechnical data CPU 313C-2 PtP CPU 313C-2 DP CPU and version CPU 313C-2 PtP and CPU 313C-2 DPMemory CPU 313C-2 PtP CPU 313C-2 DP Execution times CPU 313C-2 PtP CPU 313C-2 DPAddress areas I/O CPU 313C-2 PtP CPU 313C-2 DP Assembly CPU 313C-2 PtP CPU 313C-2 DPBlocks CPU 313C-2 PtP CPU 313C-2 DP Time-of-day CPU 313C-2 PtP CPU 313C-2 DP Technical data CPU 313C-2 PtP CPU 313C-2 DPS7 signaling functions CPU 313C-2 PtP CPU 313C-2 DP Interfaces CPU 313C-2 PtP CPU 313C-2 DP 1st interface DP master Technical data CPU 313C-2 PtP CPU 313C-2 DP DP slave GSD filePoint-to-point communication Programming CPU 313C-2 PtP CPU 313C-2 DPDimensions CPU 313C-2 PtP CPU 313C-2 DP Voltages and currents CPU 313C-2 PtP CPU 313C-2 DPTechnical data CPU 314C-2 PtP CPU 314C-2 DP CPU and version CPU 314C-2 PtP and CPU 314C-2 DPMemory CPU 314C-2 PtP CPU 314C-2 DP Execution times CPU 314C-2 PtP CPU 314C-2 DPAddress areas I/O CPU 314C-2 PtP CPU 314C-2 DP Assembly CPU 314C-2 PtP CPU 314C-2 DPBlocks CPU 314C-2 PtP CPU 314C-2 DP Time-of-day CPU 314C-2 PtP CPU 314C-2 DP Technical data CPU 314C-2 PtP CPU 314C-2 DPS7 signaling functions CPU 314C-2 PtP CPU 314C-2 DP Interfaces CPU 314C-2 PtP CPU 314C-2 DP 1st interface 2nd interface CPU 314C-2 PtP CPU 314C-2 DP Integrated I/O CPU 314C-2 PtP CPU 314C-2 DP Technical data CPU 314C-2 PtP CPU 314C-2 DP DP slaveProgramming CPU 314C-2 PtP CPU 314C-2 DP Dimensions CPU 314C-2 PtP CPU 314C-2 DP Voltages and currents CPU 314C-2 PtP CPU 314C-2 DPArrangement and usage of integrated I/Os Technical data of the integrated I/OCPU 312C Pin-out of the integrated DI/DO connector Block diagram of the integrated digital I/O Standard Interrupt Count Posi-1 Input Tioning 1L+ 2L+ Controller See also Wiring of the current/voltage inputs Analog I/OIntegrated hardware low-pass filter Maximum frequency of the input signal is 400 HzMeasurement principle Input filters software filter Principle of interference suppression with Step50 Hz interference suppression Inputs not connected Outputs not connectedParameters of standard DI ConfigurationValue range Default Range of efficiency Byte Byte 3 reservedByte 6 Byte 7 reservedParameters of standard do Parameters of standard AIThere are no parameters for standard digital outputs See also .3 in the Module Data Reference ManualParameters Value range Default Range of efficiency Parameters of standard AO\WH  \WH \WH  \WH \WH  Parameter for technological functions\WH  Interrupts Interrupt inputsStart information for OB40 Byte Variables Data type DescriptionDiagnostics Digital inputsStandard I/O Technological functionsFunctions Manual Technological functions use fast digital outputs Digital outputsFast digital outputs 13 Technical data of digital outputs CPU 31xC and CPU 31x, Technical data Technical data Module-specific data Analog inputsVoltage, currents, potentials Analog value generationEncoder selection data Interference suppression, error limitsStatus, interrupts, diagnostics Analog outputs Actuator selection data Technical data of CPU 31xC CPU 31xC and CPU 31x, Technical data Technical data of CPU Dimensions of CPUTechnical data of CPU 31x 7.1 General technical data CPU Technical data Data areas and their retentivity Technical data Technical data Communication functions Mounting dimensions W x H x D mm 40 x 125 x Weight 270 g Technical data for the CPU Technical data Data areas and their retentivity Technical data Number of entries not configurable Max Mounting dimensions W x H x D mm 40 x 125 x Weight 280 g CPU 315-2 DP Technical data Data areas and their retentivity Technical data Diagnostic buffer Yes Number of entries not configurable Max 2nd interface Technical data DP slave CPU 315-2 PN/DP Technical data Technical data Assembly Parameters of SFBs/FBs and SFC/FC of the S7 CBA at 50 % communication load Transmission speed Up to 12 Mbps Number of DP slaves 124 Profinet IO Technical data Voltages and currents CPU 317-2 DPTechnical data Timers/counters and their retentivity Technical data Technical data S7 signaling functions CPU 317-2 DPMPI DP slave Except for DP slave at both interfaces GSD file CPU 317-2 PN/DP Technical data Analog channels 4096/4096 Those local 256/256 Communication functions Routing Interface X1 configured as Yes MPI Profinet IO Technical data Voltages and currents Information about upgrading to a CPU 31xC or CPU Area of applicabilityWho should read this information? If you have used one of the following CPUs in the pastChanged behavior of certain SFCs SFC 56, SFC 57 and SFC 13 which work asynchronouslyDPV1 Hereafter calledSFC 20 Blkmov SFC 54 RddparmSFCs that may return other results Activating / deactivating DP slaves via SFCPrevious response by the CPU with Stop status New response by the CPUConverting the diagnostic addresses of DP slaves Converting the diagnostic addresses of DP slavesRuntimes that change while the program is running Runtimes that change while the program is runningReusing existing hardware configurations Reusing existing hardware configurationsReplacing a CPU 31xC/31x Replacing a CPU 31xC/31xConsistent data Routing for the CPU 31xC/31x as an intelligent slave Load memory concept for the CPU 31xC/31x10 PG/OP functions Changed retentive behavior for CPUs with firmware = Changed retentive behavior for CPUs with firmware =Procedure Asic Backup memory BusBus segment Clock flag bitsCPU Default Router Data, temporaryDeterminism DeviceDPV1 Ertec Function block Functional groundGD circuit GD elementGSD file HubIndustrial Ethernet Instance data blockInterrupt, delay Interrupt, diagnosticInterrupt, update Interrupt, processLAN MPI NCM PCNesting depth NetworkNon-isolated OB priorityPLC PNOProfibus Profibus DPProfinet Profinet AsicProfinet CBA Profinet ComponentProfinet IO Proxy Real TimeReduction factor Reference groundSFB SFCSimatic Simatic NCM PCSimatic NET SnmpStep System diagnostics TimerTimers System functionToken TopologyTwisted Pair UngroundedWAN Glossary-23Glossary-24 Index Index Index-3 Index
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