Siemens S7-300 appendix Interrupt response time, Definition of interrupt response time

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Cycle and reaction times 5.5 Interrupt response time

5.5Interrupt response time

5.5.1Overview

Definition of interrupt response time

The interrupt response time is the time that expires between the first occurrence of an interrupt signal and the call of the first interrupt OB instruction. Generally valid: Higher- priority interrupts take priority. This means that the interrupt response time is increased by the program processing time of the higher-priority interrupt OBs and the interrupt OBs of equal priority which have not yet been executed (queued).

Process/diagnostic interrupt response times of the CPUs

Table

5-13 Process/diagnostic interrupt response times

 

 

 

 

 

 

 

 

 

 

 

Process interrupt response times

Diagnostic interrupt response

 

 

 

 

 

times

 

CPU

 

external

external

Integrated I/O

Min.

Max.

 

 

min.

max.

max.

 

 

CPU

312

0.5 ms

0,8 ms

-

0.5 ms

1,0 ms

CPU

312C

0.5 ms

0,8 ms

0,6 ms

0.5 ms

1,0 ms

CPU

313C

0,4 ms

0,6 ms

0.5 ms

0,4 ms

1,0 ms

CPU

313C-2

0,4 ms

0,7 ms

0.5 ms

0,4 ms

1,0 ms

CPU

314

0,4 ms

0,7 ms

-

0,4 ms

1,0 ms

CPU

314C-2

0,4 ms

0,7 ms

0.5 ms

0,4 ms

1,0 ms

CPU

315-2 DP

0,4 ms

0,7 ms

-

0,4 ms

1,0 ms

CPU

315-2 PN/DP

 

 

 

 

 

CPU

317-2 DP

0,2 ms

0,3 ms

-

0,2 ms

0,3 ms

CPU

317-2 PN/DP

 

 

 

 

 

CPU 31xC and CPU 31x, Technical data

5-21

Manual, Edition 08/2004, A5E00105475-05

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Contents Edition 08/2004 ManualPreface Safety Guidelines Iii Purpose of the ManualRequired basic knowledge Area of applicationStandards ApprovalsCE label Tick markThis manual is part of the S7-300 documentation package Documentation classificationAdditional information required Recycling and DisposalTable of contents Table of contents Index-1 Tables Retentivity of the RAM Xii Table A-1Overview Selecting and configuringInformation on Is available Guide to the S7-300 documentation CPU performance Programming Manual From Profibus DP to Profinet Operating and display elements of CPU 31xC Operating and display elements CPU 31xCX11 X12 Integrated I/Os of CPU 31xC CPU 314C-2 PtP, for example Slot for the Simatic Micro Memory Card MMCDifferences between the CPUs Mode selector switchPower supply connection ReferenceLED designation Color Meaning Status and Error Indicators CPU 31xCOperating and display elements CPU 312, 314, 315-2 DP Operating and display elements CPUOperating and display elements Mode selector switch is used to set the CPU operating mode Operating and display elements CPU 317-2 DP Use the mode selector switch to set the CPU operating mode Operating and display elements CPU 31x-2 PN/DP Slot for the Simatic Micro Memory Card MMC General status and error displays Status and error displays of the CPUDisplays for the X1 and X2 interfaces CPU 31xC and CPU 31x, Technical data Properties InterfacesMulti-Point Interface MPI AvailabilityMPI/DP interface Profibus DP interface Devices capable of MPI communicationOperating modes for CPUs with two DP interfaces S7-300 / S7-400 with MPI interface S7-200 19.2 kbps onlyDevices capable of Profibus DP communication Connecting to Industrial EthernetRequirements Profinet IO System Devices capable of Profinet PN communicationProperties of Profinet interface See alsoDevices capable of PtP communication Point to Point PtPTransmission rate DriversOverview of communication services Communication servicesOverview of communication services Selecting the communication serviceOP communication PG communicationData exchanged by means of S7 basic communication Use as client Use in server mode forConfiguration 5 S7 communicationReduction ratio Global data communication MPI onlySend and receive conditions 315-2 PN/DP RoutingGD resources of the CPUs CPU 315-2 DPRouting network nodes MPI DP 317-2 PN/DP Routing network nodes MPI DP EthernetNumber of routed connections 2 DPRequirements Configuration in Step Real installationRouting Example of a TeleService application PtP communication With PUT/GET functions What is PROFINET??Data consistency Communication via Profinet only CPU 31x-2 PN/DPObjectives in Profinet What is Profinet CBA Component based Automation?Implementation of Profinet by us Further Information Extent of Profinet CBA and Profinet IO,2DWD9LHZ 352,17,2 Following graphic shows the new functions of Profinet IO Profinet IO System Extended Functions of Profinet IOGraphic displays Compatibility of the New Blocks Blocks in Profinet IO Chapter ContentProfinet PN New BlocksDetailed Information Compatibility of the new SSLs System status lists SSLs in Profinet IO Chapter ContentApplicability Functionality How to use open IE communicationData block for the configuration of the connection Open communication via Industrial Ethernet RequirementsCommunication interruptions DisconnectingEstablishing a connection for communication Data exchangeS7 connections Snmp communication service Availability1 S7 connection as communication path Transition point Reservation during configurationAssignment of S7 connections Connection pointsExample Allocating connection resources to Ocms servicesAssigning connections in the program Time sequence for allocation of S7 connection resourcesDistribution and availability of S7 connection resources Communication service DistributionDistribution of connection resources Resources Availability of connection resourcesTotal number Reserved for Free Connection S7 connections S7 basicExample for a CPU 317-2 PN/DP Connection resources for routingNumber of connection resources for routing Example of a CPU 314C-2 DPExtended functions of DPV1 Requirement for using the DPV1 functionality with DP slavesDPV1 Definition DPV1Functionality Interrupt blocks with DPV1 functionalitySystem blocks with DPV1 functionality Profibus DPCommunication 3.4 DPV1 Load memory Memory areas and retentivityCPU memory areas Three memory areas of your CPURetentive data in load memory Retentivity of the load memory, system memory and RAMSystem memory RAMRetentive behavior of a DB for CPUs with firmware Retentivity of memory objectsRetentive data in RAM Retentive behavior of memory objectsRUN-STOP Retentive behavior of a DB for CPUs with firmware =Address areas Description Address areas of system memoryAddress areas of system memory Process imageTime Process image updateConfigurable process image with CPU317 FW V2.3.0 or higher Retentivity of the load memory, system memory and RAM Local dataMMC as memory module for the CPU Properties of the Micro Memory Card MMCProperties of an MMC Useful life of an MMC MMC copy protectionMemory functions Memory functionsGeneral Memory functions Loading user program from Micro Memory Card MMC to the CPUDownload of new blocks or delta downloads Handling with modulesUploading blocks Compressing blocks CPU memory reset and restartCPU memory reset Deleting blocksRestart warm start Recipe Recipe n RecipesIntroduction Processing sequenceMemory concept Memory functions Measured values Measured value log filesWorking memory Evaluation of measured values Function principle Backup of project data to a Micro Memory Card MMCMemory concept Memory functions Reference Cycle time OverviewReference Execution time Time slice model Cycle timeOverview Meaning of the term cycle timeTime slices 1 ms each Sequence of cyclic program processingStep Sequence Extending the cycle time Calculating the cycle time Process image updateFactor Extending the user program processing time+ 60 μs per rack Const Portions CPUInterrupt Process Diagnostic Time-of-dayCycle control at the scan cycle check point CCP WatchdogBlock processing times may fluctuate Extension of the cycle time due to errorProgramming errors Access errors Different cycle timesExample 50 % communication load Communication loadMaximum cycle time Example 20 % communication loadInfluence on the physical cycle time Physical cycle time depending on communication loadTips Extending the OB1 cycle time Configuration during parameter assignmentCycle extension through component-based automation CBA RuntimesProfibus Base load through Profibus devices Additional marginal conditionsTips and notes Fluctuation width Update times for Profinet IOResponse time Definition of response time17 ms DP cycle times in the Profibus DP networkShortest response time is the sum Shortest response timeConditions for the shortest response time CalculationConditions for the longest response time Delay of inputs + DP cycle time at Profibus DPDelay of outputs + DP cycle time at Profibus DP Longest response timeShortest response time Longest response time Reducing the response time with direct I/O accessReducing the response time Longest response time is the sumCycle time Calculating method for calculating the cycle/response timeCycle extension through component-based automation CBA Shortest response time Longest response time Response timeInterrupt response time Process/diagnostic interrupt response times of the CPUsDefinition of interrupt response time Tv 200 μs + 1000 μs x n% Signal modulesReproducibility Reproducibility of delay interrupts and watchdog interruptsProcess interrupt processing Definition of ReproducibilityExample of cycle time calculation Sample calculationsCalculating the longest response time Sample of response time calculationCalculation of the longest response time Example of interrupt response time calculation Cycle and reaction times 5.6 Sample calculations Width General technical dataDimensions of CPU 31xC Width of CPUFollowing memory modules are available Technical data of the Micro Memory Card MMCPlug-in Simatic Micro Memory Cards Maximum number of loadable blocks in the MMCCPU 312C Technical dataData areas and their retentivity Technical dataAddress areas I/O S7 signaling functions Technical data AssemblyTesting and commissioning functions Interfaces 1st interface Communication functionsIntegrated functions Technical data FunctionalityDimensions ProgrammingCPU 313C Technical data of CPU 31xC 6.3 CPU 313CTechnical data Timers/counters and their retentivity Technical data Address areas I/O Technical data MPI KHz see the Manual Technological Functions Technical data Integrated I/OExecution times CPU 313C-2 PtP CPU 313C-2 DP Technical data CPU 313C-2 PtP CPU 313C-2 DP CPU and versionCPU 313C-2 PtP and CPU 313C-2 DP Memory CPU 313C-2 PtP CPU 313C-2 DPBlocks CPU 313C-2 PtP CPU 313C-2 DP Assembly CPU 313C-2 PtP CPU 313C-2 DPAddress areas I/O CPU 313C-2 PtP CPU 313C-2 DP S7 signaling functions CPU 313C-2 PtP CPU 313C-2 DP Technical data CPU 313C-2 PtP CPU 313C-2 DPTime-of-day CPU 313C-2 PtP CPU 313C-2 DP Interfaces CPU 313C-2 PtP CPU 313C-2 DP 1st interface DP master Programming CPU 313C-2 PtP CPU 313C-2 DP Technical data CPU 313C-2 PtP CPU 313C-2 DP DP slaveGSD file Point-to-point communicationVoltages and currents CPU 313C-2 PtP CPU 313C-2 DP Dimensions CPU 313C-2 PtP CPU 313C-2 DPExecution times CPU 314C-2 PtP CPU 314C-2 DP Technical data CPU 314C-2 PtP CPU 314C-2 DP CPU and versionCPU 314C-2 PtP and CPU 314C-2 DP Memory CPU 314C-2 PtP CPU 314C-2 DPBlocks CPU 314C-2 PtP CPU 314C-2 DP Assembly CPU 314C-2 PtP CPU 314C-2 DPAddress areas I/O CPU 314C-2 PtP CPU 314C-2 DP S7 signaling functions CPU 314C-2 PtP CPU 314C-2 DP Technical data CPU 314C-2 PtP CPU 314C-2 DPTime-of-day CPU 314C-2 PtP CPU 314C-2 DP Interfaces CPU 314C-2 PtP CPU 314C-2 DP 1st interface 2nd interface CPU 314C-2 PtP CPU 314C-2 DP Programming CPU 314C-2 PtP CPU 314C-2 DP Technical data CPU 314C-2 PtP CPU 314C-2 DP DP slaveIntegrated I/O CPU 314C-2 PtP CPU 314C-2 DP Voltages and currents CPU 314C-2 PtP CPU 314C-2 DP Dimensions CPU 314C-2 PtP CPU 314C-2 DPCPU 312C Pin-out of the integrated DI/DO connector Technical data of the integrated I/OArrangement and usage of integrated I/Os Block diagram of the integrated digital I/O Standard Interrupt Count Posi-1 Input Tioning 1L+ 2L+ Controller See also Analog I/O Wiring of the current/voltage inputsMeasurement principle Maximum frequency of the input signal is 400 HzIntegrated hardware low-pass filter Principle of interference suppression with Step Input filters software filter50 Hz interference suppression Outputs not connected Inputs not connectedValue range Default Range of efficiency ConfigurationParameters of standard DI Byte 7 reserved ByteByte 3 reserved Byte 6See also .3 in the Module Data Reference Manual Parameters of standard doParameters of standard AI There are no parameters for standard digital outputsParameters of standard AO Parameters Value range Default Range of efficiency\WH  \WH \WH  \WH \WH  Parameter for technological functions\WH  Byte Variables Data type Description InterruptsInterrupt inputs Start information for OB40Technological functions DiagnosticsDigital inputs Standard I/OFunctions Manual Fast digital outputs Digital outputsTechnological functions use fast digital outputs 13 Technical data of digital outputs CPU 31xC and CPU 31x, Technical data Analog value generation Technical data Module-specific dataAnalog inputs Voltage, currents, potentialsStatus, interrupts, diagnostics Interference suppression, error limitsEncoder selection data Analog outputs Actuator selection data Technical data of CPU 31xC CPU 31xC and CPU 31x, Technical data Dimensions of CPU Technical data of CPUTechnical data of CPU 31x 7.1 General technical data CPU Technical data Data areas and their retentivity Technical data Technical data Communication functions Mounting dimensions W x H x D mm 40 x 125 x Weight 270 g Technical data for the CPU Technical data Data areas and their retentivity Technical data Number of entries not configurable Max Mounting dimensions W x H x D mm 40 x 125 x Weight 280 g CPU 315-2 DP Technical data Data areas and their retentivity Technical data Diagnostic buffer Yes Number of entries not configurable Max 2nd interface Technical data DP slave CPU 315-2 PN/DP Technical data Technical data Assembly Parameters of SFBs/FBs and SFC/FC of the S7 CBA at 50 % communication load Transmission speed Up to 12 Mbps Number of DP slaves 124 Profinet IO CPU 317-2 DP Technical data Voltages and currentsTechnical data Timers/counters and their retentivity Technical data CPU 317-2 DP Technical data S7 signaling functionsMPI DP slave Except for DP slave at both interfaces GSD file CPU 317-2 PN/DP Technical data Analog channels 4096/4096 Those local 256/256 Communication functions Routing Interface X1 configured as Yes MPI Profinet IO Technical data Voltages and currents If you have used one of the following CPUs in the past Information about upgrading to a CPU 31xC or CPUArea of applicability Who should read this information?Hereafter called Changed behavior of certain SFCsSFC 56, SFC 57 and SFC 13 which work asynchronously DPV1SFC 54 Rddparm SFC 20 BlkmovNew response by the CPU SFCs that may return other resultsActivating / deactivating DP slaves via SFC Previous response by the CPU with Stop statusRuntimes that change while the program is running Converting the diagnostic addresses of DP slavesConverting the diagnostic addresses of DP slaves Runtimes that change while the program is runningReplacing a CPU 31xC/31x Reusing existing hardware configurationsReusing existing hardware configurations Replacing a CPU 31xC/31xConsistent data 10 PG/OP functions Load memory concept for the CPU 31xC/31xRouting for the CPU 31xC/31x as an intelligent slave Changed retentive behavior for CPUs with firmware = Changed retentive behavior for CPUs with firmware =Procedure Asic Clock flag bits Backup memoryBus Bus segmentCPU Device Default RouterData, temporary DeterminismDPV1 Ertec GD element Function blockFunctional ground GD circuitInstance data block GSD fileHub Industrial EthernetInterrupt, process Interrupt, delayInterrupt, diagnostic Interrupt, updateLAN NCM PC MPIOB priority Nesting depthNetwork Non-isolatedPNO PLCProfibus DP ProfibusProfinet Component ProfinetProfinet Asic Profinet CBAProfinet IO Reference ground ProxyReal Time Reduction factorSFC SFBSnmp SimaticSimatic NCM PC Simatic NETStep System function System diagnosticsTimer TimersUngrounded TokenTopology Twisted PairGlossary-23 WANGlossary-24 Index Index Index-3 Index
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