POST Code (Hex) | POST Routine Description |
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|
2Dh | 1 Initialize |
| 2 Put information on screen display, including Award title, CPU type, CPU speed, |
| full screen logo. |
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2Eh | Reserved |
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2Fh | Reserved |
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30h | Reserved |
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31h | Reserved |
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32h | Reserved |
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33h | Reset keyboard if Early_Reset_KB is defined e.g. Winbond 977 series Super I/O |
| chips. See also POST 63h. |
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34h | Reserved |
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35h | Test DMA Channel 0 |
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36h | Reserved |
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37h | Test DMA Channel 1 |
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38h | Reserved |
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39h | Test DMA page registers |
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3Ah | Reserved |
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3Bh | Reserved |
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3Ch | Test 8254 |
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3Dh | Reserved |
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3Eh | Test 8259 interrupt mask bits for channel 1 |
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3Fh | Reserved |
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40h | Test 8259 interrupt mask bits for channel 2 |
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41h | Reserved |
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42h | Reserved |
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43h | Test 8259 functionality |
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44h | Reserved |
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45h | Reserved |
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46h | Reserved |
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47h | Initialize EISA slot |
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48h | Reserved |
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|
49h | 1 Calculate total memory by testing the last double word of each 64K page. |
| 2 Program write allocation for AMD K5 CPU. |
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|
4Ah | Reserved |
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4Bh | Reserved |
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4Ch | Reserved |
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|
4Dh | Reserved |
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|
4Eh | 1 Program MTRR of M1 CPU |
| 2 Initialize L2 cache for P6 class CPU & program CPU with proper cacheable |
| range |
| 3 Initialize the APIC for P6 class CPU |
| 4 On MP platform, adjust the cacheable range to smaller one in case the |
| cacheable ranges between each CPU are not identical |
|
|
4Fh | Reserved |
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50h | Initialize the USB Keyboard & Mouse |
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Chapter 4 | 63 |