The following table describes each parameter under the
Parameter | Description | Options |
|
|
|
System Performance | The DRAM timing is controlled by the DRAM | Normal Mode |
| Timing Registers. The timings programmed into | Safe Mode |
| this register are dependent on the system | Fast mode |
| design. Slower rates may be required in certain | |
| Turbo Mode | |
| system designs to support loose layouts or | |
| Ultra Mode | |
| slower memory. | |
|
|
|
CAS Latency Setting | When synchronous DRAM is installed, the | 2T, 2.5T, 3T |
| number of clock cycles of CAS latency depends |
|
| on the DRAM timing. |
|
|
|
|
The other two parameters under the Advanced Chipset Features are presented below. Settings in boldface are the deafult and suggested values.
Parameter | Description | Options |
|
|
|
Memory Hole at | You can reserve this area of system memory for | Disabled |
| ISA adapter ROM. When this area is reserved, it | Enabled |
| cannot be cached. The user information of |
|
| peripherals that need to use this area of system |
|
| memory usually discuss their memory |
|
| requirements. |
|
|
|
|
AGP Aperture Size (MB) | This item lets you determine the effective size of | 64, 4,8,16,32,128 and 256. |
| the AGP Graphic Aperture. |
|
|
|
|
35 | Chapter 2 |