Yamaha YMF724F specifications OPL3 Data Register Array 0 R/W, OPL3 Data Register Array 1 R/W

Page 30

YMF724F

2-1-2. OPL3 Data Register

OPL3 Data Register Array 0 (R/W):

Address

D7

 

D6

 

D5

D4

D3

 

D2

 

D1

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00

- 01h

 

 

 

 

 

LSI TEST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

02h

 

 

 

 

 

TIMER 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

03h

 

 

 

 

 

TIMER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

04h

RST

 

MT1

 

MT2

-

-

 

-

 

ST2

ST1

 

 

 

 

 

 

 

 

 

 

 

 

 

08h

-

 

NTS

 

-

-

-

 

-

 

-

-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

- 35h

AM

 

VIB

 

EGT

KSR

 

 

 

MULT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

40

- 55h

 

KSL

 

 

 

 

TL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

- 75h

 

 

 

AR

 

 

 

 

DR

 

 

 

 

 

 

 

 

 

 

 

 

 

80

- 95h

 

 

 

SL

 

 

 

 

RR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

- A8h

 

 

 

 

 

F-NUM (L)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B0

- B8h

-

 

-

 

KON

 

BLOCK

 

 

 

F-NUM (H)

 

 

 

 

 

 

 

 

 

 

 

 

 

BDh

DAM

 

DVB

 

RHY

BD

SD

 

TOM

 

TC

HH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C0

- C8h

*

 

*

 

CHR

CHL

 

 

FB

 

 

CNT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E0

- F5h

-

 

-

 

-

-

-

 

 

 

WS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPL3 Data Register Array 1 (R/W)

Address

D7

 

D6

 

D5

D4

D3

 

D2

 

D1

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

00

- 01h

 

 

 

 

 

LSI TEST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

04h

-

 

-

 

 

 

CONNECTION SEL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

05h

-

 

-

 

-

-

-

 

*

 

*

NEW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

20

- 35h

AM

 

VIB

 

EGT

KSR

 

 

MULT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

40

- 55h

 

KSL

 

 

 

 

TL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

- 75h

 

 

 

AR

 

 

 

DR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80

- 95h

 

 

 

SL

 

 

 

RR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

- A8h

 

 

 

 

 

F-NUM (L)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B0

- B8h

-

 

-

 

KON

 

BLOCK

 

 

 

F-NUM (H)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C0

- C8h

*

 

*

 

CHR

CHL

 

 

FB

 

CNT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E0

- F5h

-

 

-

 

-

-

-

 

 

 

WS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The registers marked with * exist, but do not function.

September 21, 1998

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Image 30
Contents Features OverviewLogos GM system levelSensaura PIN Configuration YMF724F-VPIN Description PCI Bus Interface 53-pinYMF730AC-2 Interface 6-pin YMF727AC3F2 Interface 9-pin Spdif Interface 1-pinLegacy Device Interface 16-pin Power Supply 39-pin Miscellaneous 15-pinBlock Diagram OPL3System Diagram DOS VMPCI Bus Command Function OverviewPCI Configuration Register 04 05h Command 00 01h Vendor ID02 03h Device ID 06 07h Status 0Ah Sub-class Code 08h Revision ID09h Programming Interface 0Bh Base Class Code0Dh Latency Timer 0Eh Header Type10 13h PCI Audio Memory Base Address 2C-2Dh Subsystem Vendor ID 2E-2Fh Subsystem ID34h Capability Register Pointer 3Eh Minimum Grant 3Ch Interrupt Line3Dh Interrupt Pin 3Fh Maximum Latency40 41h Legacy Audio Control B76 ..........SDMA Sound Blaster DMA-8 Channel Select B108 ........SBIRQ Sound Blaster IRQ Channel SelectB1311 ......MPUIRQ MPU401 IRQ Channel Select 42 43h Extended Legacy Audio Control 44-45h Subsystem Vendor ID Write Register B1211 ......SMOD SB DMA modeB15..............IMOD Legacy IRQ mode B1413 ......SBVER SB Version Select4A-4Bh DS-1 Power Control Register 46-47h Subsystem ID Write Register48-49h DS-1 Control Register PSL1 Power Save Legacy Audio Block DPLL1 Disable PLL1 Clock OscillationPSL0 Power Save Legacy Audio Block PSN Power Save PCI Audio blockB12..............PR4 AC-2 Power down Control B13..............PR5 AC-2 Power down ControlB1514 ......AC-2 Power down Control 6 4C-4Dh D-DMA Slave Configuration 50h Capability ID52-53h Power Management Capabilities 51h Next Item PointerB10 ..........PS Power State 54-55h Power Management Control / Status58-59h Acpi Mode B0................ACPI Acpi Mode SelectISA Compatible Device OPL3PCI OPL3 Block OPL3 Status Register ROOPL3 Data Register Array 0 R/W OPL3 Data Register Array 1 R/WSound Blaster Pro Block CMD Sound Blaster Pro Mixer SB Mixer AC-2 SM Scan Mode B0................SBPDR Sound Blaster Power Down RequestSE Scan Enable Sbpda Sound Blaster Power Down AcknowledgementB70 ..........SCAN Data F1h Scan In/ Out DataF8h Interrupt Flag Register B0................SBI SB Interrupt FlagMPU401 JoystickDMA Emulation Protocol PC/PCIDMA Interrupt Routing Digital Audio InterfaceSerialized IRQ Hardware Volume Control Electrical Characteristics Absolute Maximum RatingsDC Characteristics Reset Master ClockPCI Interface Point to Point Input Hold Time for PciclkAC-2 / AC3F2 Master Clock AC-linkAC3F2 Interface Input Hold Time for AbclkAC3F2 Control Interface timing External Dimensions OFFYamaha Corporation