Yamaha YMF724F DPLL1 Disable PLL1 Clock Oscillation, PSL0 Power Save Legacy Audio Block, B10, B11

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YMF724F

b2	................DPLL1: Disable PLL1 Clock Oscillation
	Setting this bit to “1” disables the oscillation of PLL for the PCI Audio function.
	“0”: Normal	(default)
	“1”: Disable
b3	................PSL0: Power Save Legacy Audio Block 0
	Setting this bit to “1” stops providing the clock with the Legacy Audio function block 0. This block
	includes OPL3 and SB Pro engines.
	“0”: Normal	(default)
	“1”: Power Save
b4	................PSL1: Power Save Legacy Audio Block 1
	Setting this bit to “1” stops providing the clock with the Legacy Audio function block 1. This block
	includes MPU401 and Joystick.
	“0”: Normal	(default)
	“1”: Power Save
b5	................PSN: Power Save PCI Audio block
	Setting this bit to “1” stops providing the clock with the PCI Audio function block. This block includes
	PCI Audio, SRC, AC3F2 I/F, AC-2 I/F, H/W Vol. and SPDIF.
	“0”: Normal	(default)
	“1”: Power Save
b8	................PR0: AC-2 Power down Control 0

This bit controls the power state of the ADC and Input Mux in AC-2.

	“0”: Normal	(default)
	“1”: Power down
b9	................PR1: AC-2 Power down Control 1

This bit controls the power state of the DAC in AC-2.

	“0”: Normal	(default)
	“1”: Power down
b10	..............PR2: AC-2 Power down Control 2

This bit controls the power state of the Analog Mixer (Vref still on) in AC-2. This power state retains

the Reference Voltage of AC-2.

	“0”: Normal	(default)
	“1”: Power down
b11	..............PR3: AC-2 Power down Control 3

This bit controls the power state of the Analog Mixer (Vref off) in AC-2. This power state removes

Reference Voltage of AC-2.

“0”: Normal

(default)

“1”: Power down

September 21, 1998

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Contents Features OverviewGM system level LogosSensaura PIN Configuration YMF724F-VPCI Bus Interface 53-pin PIN DescriptionYMF730AC-2 Interface 6-pin Spdif Interface 1-pin YMF727AC3F2 Interface 9-pinLegacy Device Interface 16-pin Power Supply 39-pin Miscellaneous 15-pinBlock Diagram OPL3System Diagram DOS VMPCI Bus Command Function OverviewPCI Configuration Register 00 01h Vendor ID 04 05h Command02 03h Device ID 06 07h Status 0Ah Sub-class Code 08h Revision ID09h Programming Interface 0Bh Base Class Code0Eh Header Type 0Dh Latency Timer10 13h PCI Audio Memory Base Address 2E-2Fh Subsystem ID 2C-2Dh Subsystem Vendor ID34h Capability Register Pointer 3Eh Minimum Grant 3Ch Interrupt Line3Dh Interrupt Pin 3Fh Maximum Latency40 41h Legacy Audio Control B108 ........SBIRQ Sound Blaster IRQ Channel Select B76 ..........SDMA Sound Blaster DMA-8 Channel SelectB1311 ......MPUIRQ MPU401 IRQ Channel Select 42 43h Extended Legacy Audio Control 44-45h Subsystem Vendor ID Write Register B1211 ......SMOD SB DMA modeB15..............IMOD Legacy IRQ mode B1413 ......SBVER SB Version Select46-47h Subsystem ID Write Register 4A-4Bh DS-1 Power Control Register48-49h DS-1 Control Register PSL1 Power Save Legacy Audio Block DPLL1 Disable PLL1 Clock OscillationPSL0 Power Save Legacy Audio Block PSN Power Save PCI Audio blockB13..............PR5 AC-2 Power down Control B12..............PR4 AC-2 Power down ControlB1514 ......AC-2 Power down Control 6 4C-4Dh D-DMA Slave Configuration 50h Capability ID52-53h Power Management Capabilities 51h Next Item PointerB10 ..........PS Power State 54-55h Power Management Control / Status58-59h Acpi Mode B0................ACPI Acpi Mode SelectISA Compatible Device OPL3PCI OPL3 Block OPL3 Status Register ROOPL3 Data Register Array 0 R/W OPL3 Data Register Array 1 R/WSound Blaster Pro Block CMD Sound Blaster Pro Mixer SB Mixer AC-2 SM Scan Mode B0................SBPDR Sound Blaster Power Down RequestSE Scan Enable Sbpda Sound Blaster Power Down AcknowledgementB70 ..........SCAN Data F1h Scan In/ Out DataF8h Interrupt Flag Register B0................SBI SB Interrupt FlagMPU401 JoystickDMA Emulation Protocol PC/PCIDMA Digital Audio Interface Interrupt RoutingSerialized IRQ Hardware Volume Control Electrical Characteristics Absolute Maximum RatingsDC Characteristics Reset Master ClockPCI Interface Point to Point Input Hold Time for PciclkAC-2 / AC3F2 Master Clock AC-linkAC3F2 Interface Input Hold Time for AbclkAC3F2 Control Interface timing External Dimensions OFFYamaha Corporation