Yamaha YMF724F specifications 54-55h Power Management Control / Status, 58-59h Acpi Mode

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YMF724F

54-55h: Power Management Control / Status

Read / Write

Default: 0000h

Access Bus Width: 8, 16, 32-bit

 

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

 

b0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

-

-

 

-

-

-

-

-

-

-

-

-

-

-

 

PS

b[1:0] ..........PS: Power State

 

 

 

 

 

 

 

 

 

 

 

 

 

These bits determine the power state of DS-1. DS-1 supports the following power states:

 

 

 

 

 

“0”:

 

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

“1”:

 

D1

 

(not supported)

 

 

 

 

 

 

 

 

 

 

 

 

“2”:

 

D2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

“3”:

 

D3

hot

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When the power state is changed from D3hot to D0, DS-1 resets the PCI Configuration register 00-3Fh. DS-1 transits to D0 Uninitialized state.

Though the power state of this register is changed, the power consumption of DS-1 is not changed. To support low power, Windows driver controls DS-1 Power Control Register.

DS-1 can support the power state of D0, D1, D2 and D3 with ACPI. In this case, set ACPI bit (58-59h: ACPI Mode Register) to “1” to disable Capabilities of PCI Bus Power Management.

58-59h: ACPI Mode

Read / Write

Default: 0000h

Access Bus Width: 8, 16, 32-bit

 

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

 

b2

 

b1

 

b0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-

-

-

-

-

-

-

-

-

-

-

-

-

 

-

 

-

 

ACPI

b0................ACPI: ACPI Mode Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit select either PCI Bus Power Management or ACPI Mode for power management of DS-1.

 

 

 

 

“0”: PCI Bus Power Management is used. CAP bit (06-07h: Status Register) and Capabilities Pointer

 

 

 

(34h) are enabled.

(default)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

“1”: ACPI Mode is used.

CAP bit and Capabilities Pointer are hardwired “0”, and disabled.

 

 

 

 

 

September 21, 1998

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Contents Features OverviewSensaura LogosGM system level PIN Configuration YMF724F-VYMF730AC-2 Interface 6-pin PIN DescriptionPCI Bus Interface 53-pin Legacy Device Interface 16-pin YMF727AC3F2 Interface 9-pinSpdif Interface 1-pin Power Supply 39-pin Miscellaneous 15-pinBlock Diagram OPL3System Diagram DOS VMPCI Bus Command Function OverviewPCI Configuration Register 02 03h Device ID 04 05h Command00 01h Vendor ID 06 07h Status 0Ah Sub-class Code 08h Revision ID09h Programming Interface 0Bh Base Class Code10 13h PCI Audio Memory Base Address 0Dh Latency Timer0Eh Header Type 34h Capability Register Pointer 2C-2Dh Subsystem Vendor ID2E-2Fh Subsystem ID 3Eh Minimum Grant 3Ch Interrupt Line3Dh Interrupt Pin 3Fh Maximum Latency40 41h Legacy Audio Control B1311 ......MPUIRQ MPU401 IRQ Channel Select B76 ..........SDMA Sound Blaster DMA-8 Channel SelectB108 ........SBIRQ Sound Blaster IRQ Channel Select 42 43h Extended Legacy Audio Control 44-45h Subsystem Vendor ID Write Register B1211 ......SMOD SB DMA modeB15..............IMOD Legacy IRQ mode B1413 ......SBVER SB Version Select48-49h DS-1 Control Register 4A-4Bh DS-1 Power Control Register46-47h Subsystem ID Write Register PSL1 Power Save Legacy Audio Block DPLL1 Disable PLL1 Clock OscillationPSL0 Power Save Legacy Audio Block PSN Power Save PCI Audio blockB1514 ......AC-2 Power down Control 6 B12..............PR4 AC-2 Power down ControlB13..............PR5 AC-2 Power down Control 4C-4Dh D-DMA Slave Configuration 50h Capability ID52-53h Power Management Capabilities 51h Next Item PointerB10 ..........PS Power State 54-55h Power Management Control / Status58-59h Acpi Mode B0................ACPI Acpi Mode SelectISA Compatible Device OPL3PCI OPL3 Block OPL3 Status Register ROOPL3 Data Register Array 0 R/W OPL3 Data Register Array 1 R/WSound Blaster Pro Block CMD Sound Blaster Pro Mixer SB Mixer AC-2 SM Scan Mode B0................SBPDR Sound Blaster Power Down RequestSE Scan Enable Sbpda Sound Blaster Power Down AcknowledgementB70 ..........SCAN Data F1h Scan In/ Out DataF8h Interrupt Flag Register B0................SBI SB Interrupt FlagMPU401 JoystickDMA Emulation Protocol PC/PCIDMA Serialized IRQ Interrupt RoutingDigital Audio Interface Hardware Volume Control Electrical Characteristics Absolute Maximum RatingsDC Characteristics Reset Master ClockPCI Interface Point to Point Input Hold Time for PciclkAC-2 / AC3F2 Master Clock AC-linkAC3F2 Interface Input Hold Time for AbclkAC3F2 Control Interface timing External Dimensions OFFYamaha Corporation