Texas Instruments TMS320DM36X manual Reset Considerations, Interrupt Support

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2.3.2Free-Run Mode Operation

In free-run mode operation, the ADC interface performs A/D conversion continuously without stopping.

For free-run mode operation, the ADC interface should first be configured for scan mode(SCNMD), and comparator mode (CMPMD) in ADC interface control register (ADCTL), along with other configuration options. The ADC interface sets the BUSY bit in ADCTL once it is started by writing a 1 to the START bit in the ADCTL register.

Once started, the ADC interface genertaes the output after A/D conversion time. A/D conversion time is obtained by Analog switch setup time + ADC setup time + A/D conversion time.

∙Analog switch setup time = Peripheral CLK period * (SET_DIV[5:0] + 3)*2

∙ADC setup time = Peripheral CLK period * (SET_DIV[15:0] + 1)*2

∙A/D conversion time = Peripheral CLK period* (SET_DIV[5:0] + 1)*24

When the A/D scan conversion is finished for all channels, the peripheral sends an interrupt to the system (if the interrupt is enabled in ADCTL register). Note that unlike normal one-shot mode operation, another write to the START bit is not required for the one-shot mode operation to start.Once A/D conversion of all the channels is finished A/D conversion re-start from CH0.

The ADC interface is stopped during the free-run mode operation by writing '0' into START bit. After START bit turns to '0', it will be stop at the completion of current sample conversion. If user change configuration, then user need to wait at least a time which defined by SETDIV register after writing '0' into START bit. The ADC interface can also stopped during the free-run mode operatioor by reconfiguring it to one-shot mode using the SCNMD bit in ADCTL register.

2.4Reset Considerations

2.4.1Software Reset Considerations

A software reset (such as a reset generated by the emulator) causes the ADC interface registers to return to their default state after reset.

2.4.2Hardware Reset Considerations

A hardware reset of the processor causes the ADC interface registers to return to their default values after reset.

2.5Interrupt Support

2.5.1Interrupt Events and Requests

The ADC interface generates a single pulse interrupt. This interrupt is tied directly to the AINTC. ADC interface generates Scan Interrupt to CPU when A/D scan conversion is finished for all channels once.

The cause of comparator interrupt is selected according to the CMPMD bit in ADCTL register. A single common comparative data window has provided for every individual channel. Depending on the Comparator mode selected an interrupt occurs after the A/D conversion in each channel for either of the following condition.

∙Conversion data is out of the range of the comparative data window

∙Conversion data is within the range of the comparative data window

2.5.2Interrupt Multiplexing

The ADC interface is supported by the ARM Interrupt Controller (AINTC) module. The ARM_INTMUX register in the system control module must be used to select the interrupt source for multiplexed interrupts. In particular, the ADC interface interrupt is multiplexed with other interrupts. Refer to the TMS320DM365 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (SPRUFG5) for more information on the System Control Module and ARM Interrupt Controller.

10 Analog to Digital Converter (ADC) Interface SPRUFI7–March 2009

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