Contents
Preface | 5 | ||
1 | Features | 8 | |
| 1.1 | Block Diagram | 8 |
| 1.2 | Industry Compliance Statement | 9 |
2 | Peripheral Architecture | 9 | |
| 2.1 | Clock Control | 9 |
| 2.2 | Signal Descriptions | 9 |
| 2.3 | Functional Operation | 9 |
| 2.4 | Reset Considerations | 10 |
| 2.5 | Interrupt Support | 10 |
| 2.6 | EDMA Event Support | 11 |
| 2.7 | Power Management | 11 |
| 2.8 | Emulation Considerations | 11 |
3 | Registers | 11 | |
| 3.1 | ADCTL | 12 |
| 3.2 | CMPTGT | 13 |
| 3.3 | CMPLDAT | 13 |
| 3.4 | CMPUDAT | 14 |
| 3.5 | SETDIV | 14 |
| 3.6 | CHSEL | 14 |
| 3.7 | AD0DAT | 15 |
| 3.8 | AD1DAT | 15 |
| 3.9 | AD2DAT | 16 |
| 3.10 | AD3DAT | 16 |
| 3.11 | AD4DAT | 16 |
| 3.12 | AD5DAT | 17 |
| 3.13 | EMUCTRL | 17 |
Table of Contents | 3 |