Texas Instruments TMS320DM36X manual AD2DAT, 10 AD3DAT, 11 AD4DAT

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Registers

 

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Table 10. A/D Conversion Data 1 (AD1DAT) Field Descriptions

Bit

Field

Value Description

31-10

Reserved

Any writes to these bit(s) must always have a value of 0.

9-0

AD1DAT

A/D conversion data for channel 1

3.9AD2DAT

The A/D conversion data 2 (AD2DAT) register is shown in Figure 10 and described in Table 11.

Figure 10. A/D Conversion Data 2 (AD2DAT) Register

31

10

9

0

Reserved

 

 

AD2DAT

R-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

Table 11. A/D Conversion Data 2 (AD2DAT) Field Descriptions

Bit

Field

Value Description

31-10

Reserved

Any writes to these bit(s) must always have a value of 0.

9-0

AD2DAT

A/D conversion data for channel 2

3.10AD3DAT

The A/D conversion data 3 (AD3DAT) register is shown in Figure 11 and described in Table 12.

Figure 11. A/D Conversion Data 3 (AD3DAT) Register

31

10

9

0

Reserved

 

 

AD3DAT

R-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

 

 

Table 12. A/D Conversion Data 3 (AD3DAT) Field Descriptions

Bit

Field

Value Description

31-10

Reserved

Any writes to these bit(s) must always have a value of 0.

9-0

AD3DAT

A/D conversion data for channel 3

3.11AD4DAT

The A/D conversion data 4 (AD4DAT) register is shown in Figure 12 and described in Table 13.

Figure 12. A/D Conversion Data 4 (AD4DAT) Register

31

10

9

0

Reserved

 

 

AD4DAT

R-0

 

 

R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

16

Analog to Digital Converter (ADC) Interface

SPRUFI7–March 2009

 

 

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Read This First Related Documentation From Texas Instruments Related Documentation From Texas Instruments Block Diagram ADC if Block DiagramSignal Descriptions One-Shot Mode OperationIndustry Compliance Statement Clock ControlReset Considerations Interrupt SupportPower Management Edma Event SupportEmulation Considerations ADC interface Memory Map RegistersAdctl ADC Control Adctl Field DescriptionsCmptgt CmpldatComparator Target Channel Cmptgt Field Descriptions Comparison A/D Lower Data Cmpldat Field DescriptionsSetup Divide Value for Start A/D Setdiv Field Descriptions CmpudatSetdiv ChselChsel setting for Channel selection AD0DATAD1DAT Analog Input Channel Select Chsel Field DescriptionsAD2DAT 10 AD3DAT11 AD4DAT D Conversion Data 2 AD2DAT Field Descriptions12 AD5DAT EmuctrlD Conversion Data 4 AD4DAT Field Descriptions D Conversion Data 5 AD5DAT Field DescriptionsImportant Notice
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