
www.ti.com  | 
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  | Registers  | |
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  | Table 7. CHSEL setting for Channel selection | 
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CHSEL  | 
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  | Selected Channel  | 
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000001b  | 
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  | Channel 0  | 
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000010b  | 
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  | Channel 1  | 
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000100b  | 
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  | Channel 2  | 
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001000b  | 
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  | Channel 3  | 
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010000b  | 
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  | Channel 4  | 
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100000b  | 
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  | Channel 5  | 
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  | Figure 7. Analog Input Channel Select (CHSEL) Register | 
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31  | 
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  | 6  | 5  | 0  | 
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  | Reserved  | 
  | CHSEL  | 
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LEGEND: R/W = Read/Write; R = Read only;   | 
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  | Table 8. Analog Input Channel Select (CHSEL) Field Descriptions | 
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Bit  | Field  | Value  | Description  | 
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Reserved  | 0  | Any writes to these bit(s) must always have a value of 0.  | 
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CHSEL  | 
  | A/D conversion select bit  | 
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  | 0  | Analog Input unselected  | 
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  | 1  | Analog Input selected  | 
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3.7AD0DAT
The A/D conversion data 0 (AD0DAT) register is shown in Figure 8 and descried in Table 9.
Figure 8. A/D Conversion Data 0 (AD0DAT) Register
31  | 10  | 9  | 0  | 
Reserved  | 
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  | AD0DAT  | 
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LEGEND: R/W = Read/Write; R = Read only; 
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  | Table 9. A/D Conversion Data 0 (AD0DAT) Field Descriptions | 
Bit | Field  | Value Description  | 
Reserved  | Any writes to these bit(s) must always have a value of 0.  | |
AD0DAT  | A/D conversion data for channel 0  | 
3.8AD1DAT
The A/D conversion data 1 (AD1DAT) register is shown in Figure 9 and described in Table 10.
Figure 9. A/D Conversion Data 1 (AD1DAT) Register
31  | 10  | 9  | 0  | 
Reserved  | 
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  | AD1DAT  | 
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LEGEND: R/W = Read/Write; R = Read only; 
Analog to Digital Converter (ADC) Interface  | 15  | |
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