Registers | www.ti.com |
3.1ADCTL
The ADC control register (ADCTL) is shown in Figure 2 and described in Table 2.
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| Figure 2. ADC Control (ADCTL) Register |
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| 31 |
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| 24 |
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| Reserved |
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| 23 |
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| 16 |
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| Reserved |
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| 15 |
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| 8 |
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| Reserved |
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| 7 |
| 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| BUSY | CMPFLG | CMPIEN | CMPMD | SCNFLG | SCNIEN | SCNMD | START | |
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LEGEND: R/W = Read/Write; R = Read only; |
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| Table 2. ADC Control (ADCTL) Field Descriptions |
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| Bit | Field | Value | Description |
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| Reserved |
| Any writes to these bit(s) must always have a value of 0. |
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| 7 | BUSY |
| Busy flag |
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| 6 | CMPFLG |
| Comparator interrupt flag clear bit. Writing ‘1’ into this bit clears the comparator interrupt flag and | |||||
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| then it will be cleared automatically. At read time, comparator interrupt status can be read. | |||||
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| 0 | No interrupt |
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| 1 | Interrupt |
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| 5 | CMPIEN |
| Comparator interrupt enable bit |
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| 0 | Disable |
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| 1 | Enable |
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| 4 | CMPMD |
| Comparator mode select bit |
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| 0 | If the value of A/D input data is larger or smaller than the comparative data, a comparator interrupt | |||||
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| is generated. ADC input data < CMPLDAT or ADC input data > CMPUDAT |
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| 1 | If the value of A/D input data is within the range of the comparative data, a comparator interrupt is | |||||
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| generated. CMPLDAT ≤ ADC input data ≤ CMPUDAT |
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| 3 | SCNFLG |
| Scan interrupt flag clear bit. Writing '1' into this bit clears the scan interrupt flag then it will be | |||||
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| cleared automatically. At read time, scan interrupt status can be read. |
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| 0 | No interrupt |
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| 1 | Interrupt |
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| 2 | SCNIEN |
| Scan interrupt enable bit |
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| 0 | Disable |
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| 1 | Enable |
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| 1 | SCNMD |
| Scan mode selection |
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| 0 | One shot |
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| 1 | Free run |
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| 0 | START |
| A/D conversion start bit The status is cleared automatically when A/D conversion in | |||||
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| terminates. Writing '0' into this bit in | |||||
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| the time of | |||||
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| only at the time of A/D conversion.) |
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12 | Analog to Digital Converter (ADC) Interface |
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