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Texas Instruments TMS320TCI648x Functional Operation, Pin Description, Component Block Diagram

Models: TMS320TCI648x

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SRIO Functional Description

Table 4. Pin Description

	Pin	Signal
Pin Name	Count	Direction	Description
RIOTX3/ RIOTX3	2	Output	Transmit Data – Differential point-to-point unidirectional bus. Transmits
			packet data to a receiving device’s RX pins. Most significant bits in 1
			port 4X device. Used in 4 port 1X device.
RIOTX2/ RIOTX2	2	Output	Transmit Data – Differential point-to-point unidirectional bus. Transmits
			packet data to a receiving device’s RX pins. Bit used in 4 port 1x
			device and 1 port 4X device.
RIOTX1/ RIOTX1	2	Output	Transmit Data – Differential point-to-point unidirectional bus. Transmits
			packet data to a receiving device’s RX pins. Bit used in 4 port 1x
			device and 1 port 4X device.
RIOTX0/ RIOTX0	2	Output	Transmit Data – Differential point-to-point unidirectional bus. Transmits
			packet data to a receiving device’s RX pins. Bit used in 1 port 1X
			device, 4 port 1x device, and 1 port 4X device.
RIORX3/ RIORX3	2	Input	Receive Data – Differential point-to-point unidirectional bus. Receives
			packet data for a transmitting device’s TX pins. Most significant bits in
			1 port 4X device. Used in 4 port 1X device.
RIORX2/ RIORX2	2	Input	Receive Data – Differential point-to-point unidirectional bus. Receives
			packet data for a transmitting device’s TX pins. Bit used in 4 port 1x
			device and 1 port 4X device.
RIORX1/ RIORX1	2	Input	Receive Data – Differential point-to-point unidirectional bus. Receives
			packet data for a transmitting device’s TX pins. Bit used in 4 port 1x
			device and 1 port 4X device.
RIORX0/ RIORX0	2	Input	Receive Data – Differential point-to-point unidirectional bus. Receives
			packet data for a transmitting device’s TX pins. Bit used in 1 port 1X
			device, 4 port 1x device, and 1 port 4X device.
RIOCLK/ RIOCLK	2	Input	Reference Clock Input Buffer for peripheral clock recovery circuitry.

2.3Functional Operation

2.3.1Component Block Diagram

Figure 8 shows a component block diagram of the SRIO peripheral. The load/store unit (LSU) controls the transmission of direct I/O packets, and the memory access unit (MAU) controls the reception of direct I/O packets. The LSU also controls the transmission of maintenance packets. Message packets are transmitted by the TXU and received by the RXU. These four units use the internal DMA to communicate with internal memory, and they use buffers and receive/transmit ports to communicate with external devices. Serializer/deserializer (SERDES) macros support the ports by performing the parallel-to-serial coding for transmission and serial-to-parallel decoding for reception.

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Serial RapidIO (SRIO)

SPRUE13A –September 2006

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Texas Instruments TMS320TCI648x manual Functional Operation, Pin Description, Component Block Diagram

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticsr Port Link Maintenance Request CSR n SP n Lmreq List of Figures INTDSTnRATECNTL Interrupt Rate Control Register Transmit Cppi Supported Flow Mask Registers Port-Write-In Capture CSRs List of Tables PF16BCNTL Registers LSUnREG6 Registers and the Associated LSUs SP n Errdet Registers and the Associated Ports Read This First Trademarks General RapidIO System RapidIO Architectural HierarchyOverview Physical Layer 1x/4x LP-Serial Specification RapidIO Interconnect ArchitectureRapidIO Feature Support in Srio Features Supported in Srio PeripheralTI Devices Supported By This Document Features Not SupportedStandards External Devices Requirements TI Devices Supported By This DocumentRegisters Checked for Multicast DeviceID OverviewPeripheral Data Flow Registers Checked For Multicast DeviceIDSrio Packets Operation SequenceOperation Sequence Example Packet Streaming WriteControl Symbols 4x RapidIO Packet Data Stream Streaming-Write ClassPacket Types Srio PinsSrio Packet Type Ftype Ttype Packet TypePin Description Component Block DiagramFunctional Operation Srio Component Block Diagram MPY Enpll Serdes Macro and its ConfigurationsEnabling the PLL Bit Field Value Description MPYFrequency Range versus MPY Value Line Rate versus PLL Output Clock FrequencyEffect of the Rate Bits Enabling the ReceiverBit Field CDRLOS Align Term Invpair Rate Buswidth Enrx LOS CFGRX22-19 EQ BitsEnabling the Transmitter Amplitude Reduction DE Bits of SERDESCFGTXnCNTLSwing DE BitsDirect I/O Operation Serdes Configuration ExampleSwing Bits of SERDESCFGTXnCNTL Swing BitsLSU Control/Command Register Fields LSU Register Field RapidIO Packet Header FieldBSY LSU Status Register FieldsLSU Register Field Function LSU Registers Timing Example Burst Nwriter Detailed Data Path DescriptionDirect I/O TX Operation Write TransactionsRead Transactions Segmentation Direct I/O RX OperationReset and Power Down State Message PassingRX Operation Cppi RX Scheme for RapidIOMessage Request Packet Mailbox to Queue Mapping Register H n Rxumaph n RX DMA State Completion Pointer CP Address Offset 680h-6BChMailbox to Queue Mapping Register L n Rxumapl n Bit Name DescriptionRX Buffer Descriptor Field Descriptions Field DescriptionDSP core uses this bit to reclaim buffers RX Cppi Mode Explanation Srio Functional Description Cppi Boundary Diagram TX OperationTX DMA State Completion Pointer CP Address Offset 58h-5BCh TX Buffer Descriptor Field DefinitionsTX Buffer Descriptor Field Definitions Field DescriptionSsize Srio Functional Description TXQUEUECNTL2 Address Offset 7E8h TXQUEUECNTL0 Address Offset 7E0hTXQUEUECNTL1 Address Offset 7E4h TXQUEUECNTL3 Address Offset 7EChTXQUEUECNTL111-8 TXQUEUECNTL13-0TXQUEUECNTL17-4 TXQUEUECNTL23-0TXQUEUECNTL311-8 TXQUEUECNTL33-0TXQUEUECNTL37-4 Reset and Power Down State TX Operation Message Passing Software RequirementsRX Operation RX Buffer Descriptor Initialization ExampleQueue Mapping RX Buffer Descriptors TX Buffer DescriptorDoorbell Operation MaintenanceStart Message Passing Reg # Examples of Doorbellinfo Designations See FigureInfo Field Segments Bit LSUnREG5Atomic Operations Congestion ControlDetailed Description Flowcntlid FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0Endianness FL9Translation for MMR space Endian Conversion TMS320TCI6482Bus Reset and Power DownReset Hierarchy Logical BlockReset and Power Down Summary Enable and Enable Status RegistersGlobal Enable and Global Enable Status Field Descriptions RegisterBit Field Block Enable and Block Enable Status Field DescriptionsEnstat Valu Description ePeripheral Control Register PCR Field Descriptions Software Shutdown DetailsEmulation Peren Soft FreeMultiple Ports With 1x Operation Peripheral Control Register PCR Field DescriptionsTX Buffers, Credit, and Packet Reordering Single Port With 1x or 4x Operation Unavailable Outbound Credit13.2 PLL, Ports, Device ID and Data Rate Initializations Port Mode Register SettingsEnabling the Srio Peripheral Peripheral Initializations Set Device ID RegistersConfiguration and Operation Assert the Peren bit to enable logical layer data flowBootload Capability Read register to check portx1-4 OK bitRX Multicast Support Bootload Data MovementDevice Wakeup Enabling Multicast and Packet Forwarding Multicast DeviceID OperationDaisy Chain Operation and Packet Forwarding 16BITDEVIDUPBOUND 16BITDEVIDLOWBOUND8BITDEVIDUPBOUND OutboundPort 8BITDEVIDLOWBOUNDFor an LSU or the TXU For the MAU or the RXURxiodmaaccess MsgreqtimeoutPktrspnstimeout UnsolicitedrspnsCPU Interrupts General DescriptionInterrupt Condition Status and Clear Registers Interrupt Condition Status and Clear Bits Doorbell Interrupt Condition Status and Clear RegistersDoorbell 2 Interrupt Condition Status and Clear Registers Cppi Interrupt Condition Status and Clear RegistersRX Cppi Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status and Clear RegistersLSU3 Bit Associated LSU Interrupt ConditionLSU4 LSU2ICC11 ICC10 ICC9 ICC8 ICS11 ICS10 ICS9 ICS8ICS2 ICS1 ICS0 ICC2 ICC1 ICC01st Step Nd Step 3rd Step Interrupt Clearing Sequence for Special Event InterruptsInterrupt Function Doorbell Interrupt Condition Routing Registers Interrupt Condition Routing RegistersInterrupt Condition Routing Options Interrupt Function St Step Nd Step Rd StepICR3 ICR2 ICR1 ICR0 Cppi Interrupt Condition Routing RegistersICR7 ICR6 ICR5 ICR4 ICR15 ICR14 ICR13 ICR12TX Cppi Interrupt Condition Routing Registers LSU Interrupt Condition Routing RegistersICR31 ICR30 ICR29 ICR28 ICR23 ICR22 ICR21 ICR20ICR19 ICR18 ICR17 ICR16 ICR27 ICR26 ICR25 ICR24Interrupt Status Decode Registers ICR2 ICR1 ICR0Interrupt Status Decode Register INTDSTnDECODE Interrupt Generation Interrupt PacingInterrupt Handling INTDSTnRATECNTL Interrupt Rate Control Register101 Offset Acronym Register Description IntroductionSerial RapidIO Srio Registers Serial RapidIO Srio Registers Offset Acronym Register DescriptionINTDST5DECODE INTDST3DECODEINTDST4DECODE INTDST6DECODEQUEUE1TXDMAHDP QUEUE1RXDMACP QUEUE15RXDMAHDPQUEUE0RXDMACP QUEUE2RXDMACPRXUMAPL8 RXUMAPL7RXUMAPH7 RXUMAPH8RXUMAPL31 RXUMAPL30RXUMAPH30 RXUMAPH31SP1CTL SP1SILENCETIMER SpipdiscoverytimerSP0SILENCETIMER SP2SILENCETIMERType Peripheral Identification Register PIDPeripheral ID Register PID Field Descriptions Class REVPeripheral Control Register PCR HaltsPeripheral Settings Control Register Persetcntl Prescalerselect Enable Serdes PLL Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field DescriptionsPeripheral Global Enable Status Register Gblenstat MMRs for the Srio peripheral Block n Enable Register BLKnEN Field Descriptions Block n Enable Register BLKnENBlock n Enable Registers and the Associated Blocks Register Address Offset Associated BlockBlock n Enable Status Register BLKnENSTAT Block n Enable Status Registers and the Associated Blocks8BNODEID RapidIO DEVICEID1 Register DEVICEIDREG1RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions 16BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field DescriptionsPF16BCNTL Registers Register Address OffsetPacket Forwarding Register n for 8-Bit Device IDs PF8BCNTLn PF8BCNTL RegistersSERDESCFGRXnCNTL Registers and the Associated Ports Register Address Offset Associated PortVia a 50 pF capacitor to Vssa 127 Swing Invpair Rate Buswidth Entx SERDESCFGTXnCNTL Registers and the Associated PortsSERDESCFGTX3CNTL 129 Serdes Macro Configuration Register n SERDESCFGnCNTL SERDESCFGnCNTL Registers and the Associated Ports131 DOORBELLn Interrupt Condition Status Register DOORBELLnICSR Doorbell nICSR RegistersDOORBELLn Interrupt Condition Clear Register DOORBELLnICCR Doorbell nICCR RegistersRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr LSU Interrupt Condition Status Register Lsuicsr ICS31139 140 LSU Interrupt Condition Clear Register Lsuiccr 31-17 Reserved These reserved bits return 0s when read Errrstevnticcr Field Descriptions Doorbell nICRR Registers Field Value Description= 0 to Eight interrupt destinations INTDST0-INTDST7 146 LSU Interrupt Condition Routing Registers LSUICRR0-LSUICRR3 LSU Interrupt Condition Routing Register Field Descriptions = 0 to 2, 8 to 11, Interrupt destinations INTDST0-INTDST7 Interrupt Status Decode Register INTDSTnDECODE DestinationTX buffer descriptor queue 4 bit 4 of Txcppiicsr ∙ Doorbell 0, bit 15 bit 15 of DOORBELL0ICSR ISD1 ISD3ISD2 INTDSTn Interrupt Rate Control Register INTDSTnRATECNTL CountdownvalueLSUn Control Register 0 LSUnREG0 Field Descriptions LSUn Control Register 0 LSUnREG0LSUnREG0 Registers and the Associated LSUs AddressmsbLSUnREG1 Registers and the Associated LSUs For packet type 8 maintenance packetLSUn Control Register 1 LSUnREG1 LSUn Control Register 1 LSUnREG1 Field DescriptionsLSUn Control Register 2 LSUnREG2 Field Descriptions LSUn Control Register 2 LSUnREG2LSUnREG2 Registers and the Associated LSUs DspaddressLSUn Control Register 3 LSUnREG3 Field Descriptions LSUn Control Register 3 LSUnREG3LSUnREG3 Registers and the Associated LSUs BytecountLSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 4 LSUnREG4LSUnREG4 Registers and the Associated LSUs LSUn Control Register 5 LSUnREG5 Field Descriptions LSUn Control Register 5 LSUnREG5LSUnREG5 Registers and the Associated LSUs LSUn Control Register 6 LSUnREG6 Field Descriptions LSUn Control Register 6 LSUnREG6LSUnREG6 Registers and the Associated LSUs Completioncode BSYLSUn Congestion Control Flow Mask Register LSUnFLOWMASKS LSUnFLOWMASKS Registers and the Associated LSUsLSU n supports Flow 8 from table entry QUEUEnTXDMAHDP Registers RegisterQUEUEnTXDMACP Registers QUEUEnRXDMAHDP Registers QUEUEnRXDMACP Registers RxcpTransmit Queue Teardown Register Txqueueteardown Txcppiflowmasks Registers and the Associated TX Queues TX Queue n Flowmask Field Descriptions Queue n supports Flow 12 from table entry Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field DescriptionsTXQUEUECNTL2 Address Offset 07E8h TXQUEUECNTL0 Address Offset 07E0hTXQUEUECNTL1 Address Offset 07E4h TXQUEUECNTL3 Address Offset 07EChField Pair TXQUEUECNTL211-8 Mailbox to Queue Mapping Registers RXUMAPLn and RXUMAPHn 0890h Mapper For a multi-segment message LettermaskFor a single-segment message LetterQueueid SegmentmappingFlow Control Table Entry Register n FLOWCNTLn Flowcntl n RegistersDeviceidentity Devicevendoridentity Device Identity CAR DevidDevice Identity CAR Devid Field Descriptions DeviceidentityDevicerev Device Information CAR DevinfoDevice Information CAR Devinfo Field Descriptions 31-0Assyidentity Assyvendoridentity Assembly Identity CAR AsblyidAssembly Identity CAR Asblyid Field Descriptions AssyidentityExtendedfeaturesptr Assembly Information CAR AsblyinfoAssembly Information CAR Asblyinfo Field Descriptions AssyrevProcessing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field DescriptionsSource and target of an operation. All PEs shall at minimum Source Operations CAR Srcop Source Operations CAR Srcop Field DescriptionsRead Write Streamwrite Writewith Datamess Doorbell Destination Operations CAR DestopDestination Operations CAR Destop Field Descriptions Resp Andswap AtomicExtendedaddressingcontrol Processing Element Logical Layer Control CSR PellctlAddressing Bit Field Value Local Configuration Space Base Address 0 CSR LclcfghbarLcsba Local Configuration Space Base Address 1 CSR Lclcfgbar Basedeviceid Base Device ID CSR BaseidBase Device ID CSR Baseid Field Descriptions LargebasedeviceidHost Base Device ID Lock CSR Hostbaseidlock HostbasedeviceidComponenttag Component Tag CSR ComptagComponent Tag CSR Comptag Field Descriptions Efptr Efid EfptrPort Link Time-Out Control CSR Spltctl Port Link Timeout Control CSR Spltctl Field DescriptionsTimeoutvalue Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Port General Control CSR Spgenctl Field DescriptionsSPnLMREQ Registers and the Associated Ports Port Link Maintenance Request CSR n SPnLMREQCommand SP2LMREQPort Link Maintenance Response CSR n SPnLMRESP SPnLMRESP Registers and the Associated PortsPort Local AckID Status CSR n SPnACKIDSTAT SPnACKIDSTAT Registers and the Associated PortsSPnERRSTAT Registers and the Associated Ports Port Error and Status CSR n SPnERRSTATPort Error and Status CSR n SPnERRSTAT Field Descriptions Inputerrorenc OutputerrorencOutputerrorstp InputerrorstpPortok PortuninitializedPort Control CSR n SPnCTL Field Descriptions Port Control CSR n SPnCTLSPnCTL Registers and the Associated Ports Inputportenable PortdisableOutputportenable ErrorcheckdisableRather than a parallel port Error Reporting Block Header Register Errrptbh Logical/Transport Layer Error Detect CSR Errdet RX I/O DMA access error Logical/Transport Layer Error Enable CSR Erren Unsupportedtransenable PktresptimeoutenableUnsolicitedrespenable RxcppisecurityenableLogical/Transport Layer High Address Capture CSR Haddrcapt ADDRESS6332Xamsbs Logical/Transport Layer Address Capture CSR AddrcaptADDRESS313 Msbsourceid Sourceid Logical/Transport Layer Device ID Capture CSR IdcaptMsbdestid Destid MsbdestidImpspecific Logical/Transport Layer Control Capture CSR CtrlcaptFtype Ttype Msginfo FtypeDeviceidmsb Port-Write Target Device ID CSR PwtgtidPort-Write Target Device ID CSR Pwtgtid Field Descriptions DeviceidSPnERRDET Registers and the Associated Ports Port Error Detect CSR n SPnERRDETPort Error Detect CSR n SPnERRDET Field Descriptions Linktimeout ProtocolerrorDelineationerror RcvdpktnotaccptSPnRATEEN Registers and the Associated Ports Port Error Rate Enable CSR n SPnRATEENPort Error Rate Enable CSR n SPnRATEEN Field Descriptions Linktimeouten ProtocolerrorenDelineationerroren PktunexpectedackidenPort n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 SPnERRATTRCAPTDBG0 Registers and the Associated PortsCase of a packet error Port n Error Capture CSR 1 SPnERRCAPTDBG1Description Case of a control-symbol error SPnERRCAPTDBG1 Registers and the Associated PortsPort n Error Capture CSR 2 SPnERRCAPTDBG2 SPnERRCAPTDBG2 Registers and the Associated PortsPort n Error Capture CSR 3 SPnERRCAPTDBG3 SPnERRCAPTDBG3 Registers and the Associated PortsPort n Error Capture CSR 4 SPnERRCAPTDBG4 SPnERRCAPTDBG4 Registers and the Associated PortsSPnERRRATE Registers and the Associated Ports Port Error Rate CSR n SPnERRRATEPort Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate Threshold CSR n SPnERRTHRESH SPnERRTHRESH Registers and the Associated PortsDiscoverytimer PwtimerPort IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field DescriptionsPwen RstenRstcs PwirqPrescale Port IP Prescaler Register IpprescalPort IP Prescaler Register Ipprescal Field Descriptions Port-Write-In Capture CSRs SPIPPWINCAPT0-3 Port-Write-In Capture CSR Field DescriptionsSPnRSTOPT Registers and the Associated Ports Port Reset Option CSR n SPnRSTOPTPort Reset Option CSR n SPnRSTOPT Field Descriptions PortidPort Control Independent Register n SPnCTLINDEP SPnCTLINDEP Registers and the Associated PortsIlltranserr SenddbgpktIlltransen MaxretryenSilencetimer Port Silence Timer n Register SPnSILENCETIMERSPnSILENCETIMER Registers and the Associated Ports Bit Field Value Description 31-0 SPnMULTEVNTCS Registers and the Associated PortsMultevntcs STYPE0 PAR0 PAR1 STYPE1 CMD Csemb Port Control Symbol Transmit n Register SPnCSTXSPnCSTX Registers and the Associated Ports STYPE0Index Comptag Ctrlcapt Devinfo Pellctl Haddrcapt Lsuicsr 237 Pefeat 232 Srio Registers Rxcppicntl Rxcppiiccr Rxcppiicrr RXCPPIICRR2 Rxcppiicsr Broken link Degraded link Maximum retry error at port n Txqueueteardown Xoff Xon Important Notice