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Interrupt Conditions
The interrupt status bits found in the ERR_RST_EVNT (0x0270) can be cleared by writing to the ICCR register (0x0278) in the same manner as other interrupts. However, in order for new event detection and interrupt generation to occur for these special interrupts, additional register bits must be cleared. The following table notes the additional interrupt source register bits that need to be cleared and the appropriated sequence. These are all the bits that can cause the ERR_RST_EVNT status bits to be set
Table 38. Interrupt Clearing Sequence for Special Event Interrupts
Interrupt Function
Multicast Event Control Symbol received on any port
Port Write In Request received on any port
Port 0 Error
Port 1 Error
Port 2 Error
(TMS320TCI6482 Only)
92Serial RapidIO (SRIO)
1st Step | 2 nd Step | 3rd Step |
Write 1 to clear: | Write 1 to clear: |
|
Offset 0x0278 | Offset 0x12004 |
|
ERR_RST_EVNT_ICCR[0] | SP_IP_MODE[4] |
|
Write 1 to clear: | Write 1 to clear: |
|
Offset 0x0278 | Offset 0x12004 |
|
ERR_RST_EVNT_ICCR[1] | SP_IP_MODE[0] |
|
Write 1 to clear: | Write 1 to clear any of the | Write 1 to clear: |
| following possible bits: |
|
Offset 0x0278 | Offset 0x2040 | Offset 0x14004 |
ERR_RST_EVNT_ICCR[8] | SP0_ERR_STAT[2] – Fatal | SP0_CTL_INDEP[6] |
| error |
|
| SP0_ERR_STAT[25] – Failed |
|
| Threshold |
|
| SP0_ERR_STAT[24] – |
|
| Degraded Threshold |
|
| Offset 0x14004 |
|
| SP0_CTL_INDEP[20] – Illegal |
|
| Transaction |
|
| SP0_CTL_INDEP[16] – Max |
|
| Retry Error |
|
Write 1 to clear: | Write 1 to clear any of the | Write 1 to clear: |
| following possible bits: |
|
Offset 0x0278 | Offset 0x2080 | Offset 0x14104 |
ERR_RST_EVNT_ICCR[9] | SP1_ERR_STAT[2] – Fatal | SP1_CTL_INDEP[6] |
| error |
|
| SP1_ERR_STAT[25] – Failed |
|
| Threshold |
|
| SP1_ERR_STAT[24] – |
|
| Degraded Threshold |
|
| Offset 0x14104 |
|
| SP1_CTL_INDEP[20] – Illegal |
|
| Transaction |
|
| SP1_CTL_INDEP[16] – Max |
|
| Retry Error |
|
Write 1 to clear: | Write 1 to clear any of the | Write 1 to clear: |
| following possible bits: |
|
Offset 0x0278 | Offset 0x20C0 | Offset 0x14204 |
ERR_RST_EVNT_ICCR[10] | SP2_ERR_STAT[2] – Fatal | SP2_CTL_INDEP[6] |
| error |
|
| SP2_ERR_STAT[25] – Failed |
|
| Threshold |
|
| SP2_ERR_STAT[24] – |
|
| Degraded Threshold |
|
| Offset 0x14204 |
|
| SP2_CTL_INDEP[20] – Illegal |
|
| Transaction |
|
| SP2_CTL_INDEP[16] – Max |
|
| Retry Error |
|
SPRUE13A
