Texas Instruments TMS320TCI648x specification

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SRIO Registers

5.76 Logical/Transport Layer Error Enable CSR (ERR_EN)

The logical/transport layer error enable CSR (ERR_EN) is shown in Figure 139 and described in Table 152.

Figure 139. Logical/Transport Layer Error Enable CSR (ERR_EN) - Address Offset 200Ch

31	30	29	28	27	26	25	24
IO_ERR_	MSG_ERR_	Reserved	ERR_MSG_	ILL_TRANS_	Reserved	MSG_REQ_ PKT_RESP_
RESP_	RESP_	(write 0)	FORMAT_	DECODE_	(write 0)	TIMEOUT_	TIMEOUT_
ENABLE	ENABLE		ENABLE	ENABLE		ENABLE	ENABLE
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
23	22	21
UNSOLICITED_	UNSUPPORTED_				Reserved
RESP_ENABLE	TRANS_ENABLE
R/W-0	R/W-0				R-0
							8
			Reserved
				R-0
7	6	5					0
RX_CPPI_	RX_IO_				Reserved
SECURITY_	SECURITY_
ENABLE	ENABLE
R/W-0	R/W-0				R-0

LEGEND: R/W = Read/Write; R = Read only; -n= Value after reset

Table 152. Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions

	Bit	Field	Value	Description
	31	IO_ERR_RESP_ENABLE		IO error response reporting enable
			0	Disable reporting of an IO error response.
			1	Enable reporting of an IO error response (endpoint device only).
				Save and lock original request transaction capture information in all
				Logical/Transport Layer Capture CSRs.
	30	MSG_ERR_RESP_ENABLE		Message error response reporting enable
			0	Disable reporting of a message error response.
			1	Enable reporting of a message error response (endpoint device
				only). Save and lock transaction capture information in all
				Logical/Transport Layer Capture CSRs.
	29	Reserved	0	Always write 0 to this reserved bit.
	28	ERR_MSG_FORMAT_ENABLE		Message format error reporting enable
			0	Disable reporting of a message format error.
			1	Enable reporting of a message format error (endpoint device only).
				Save and lock transaction capture information in Logical/Transport
				Layer Device ID and Control Capture CSRs.
	27	ILL_TRANS_DECODE_ENABLE		Illegal transaction decode error reporting enable
			0	Disable reporting of an illegal transaction decode error.
			1	Enable reporting of an illegal transaction decode error (switch or
				endpoint device). Save and lock transaction capture information in
				Logical/Transport Layer Device ID and Control Capture CSRs.
	26	Reserved	0	Always write 0 to this reserved bit.
	25	MSG_REQ_TIMEOUT_ENABLE		Message request time-out error reporting enable
			0	Disable reporting of a message request time-out error.
			1	Enable reporting of a message request time-out error (endpoint
				device only). Save and lock transaction capture information in
				Logical/Transport Layer Device ID and Control Capture CSRs for the
				last message-segment request packet received.
212	Serial RapidIO (SRIO)			SPRUE13A –September 2006

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Texas Instruments TMS320TCI648x manual Logical/Transport Layer Error Enable CSR Erren

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticsr Port Link Maintenance Request CSR n SP n Lmreq List of Figures INTDSTnRATECNTL Interrupt Rate Control Register Transmit Cppi Supported Flow Mask Registers Port-Write-In Capture CSRs List of Tables PF16BCNTL Registers LSUnREG6 Registers and the Associated LSUs SP n Errdet Registers and the Associated Ports Read This First Trademarks General RapidIO System RapidIO Architectural Hierarchy Overview Physical Layer 1x/4x LP-Serial Specification RapidIO Interconnect Architecture RapidIO Feature Support in Srio Features Supported in Srio Peripheral Features Not Supported Standards External Devices RequirementsTI Devices Supported By This Document TI Devices Supported By This Document Overview Peripheral Data FlowRegisters Checked for Multicast DeviceID Registers Checked For Multicast DeviceID Srio Packets Operation Sequence Operation Sequence Example Packet Streaming Write Control Symbols 4x RapidIO Packet Data Stream Streaming-Write Class Srio Pins Srio Packet TypePacket Types Ftype Ttype Packet Type Pin Description Component Block DiagramFunctional Operation Srio Component Block Diagram MPY Enpll Serdes Macro and its ConfigurationsEnabling the PLL Bit Field Value Description MPY Line Rate versus PLL Output Clock Frequency Effect of the Rate BitsFrequency Range versus MPY Value Enabling the Receiver Bit Field CDRLOS Align Term Invpair Rate Buswidth Enrx LOS CFGRX22-19 EQ BitsEnabling the Transmitter DE Bits of SERDESCFGTXnCNTL SwingAmplitude Reduction DE Bits Serdes Configuration Example Swing Bits of SERDESCFGTXnCNTLDirect I/O Operation Swing Bits LSU Control/Command Register Fields LSU Register Field RapidIO Packet Header Field BSY LSU Status Register FieldsLSU Register Field Function LSU Registers Timing Example Burst Nwriter Detailed Data Path Description Direct I/O TX Operation Write Transactions Read Transactions Segmentation Direct I/O RX Operation Reset and Power Down State Message Passing RX Operation Cppi RX Scheme for RapidIO Message Request Packet RX DMA State Completion Pointer CP Address Offset 680h-6BCh Mailbox to Queue Mapping Register L n Rxumapl nMailbox to Queue Mapping Register H n Rxumaph n Bit Name Description RX Buffer Descriptor Field Descriptions Field Description DSP core uses this bit to reclaim buffers RX Cppi Mode Explanation Srio Functional Description Cppi Boundary Diagram TX Operation TX DMA State Completion Pointer CP Address Offset 58h-5BCh TX Buffer Descriptor Field Definitions TX Buffer Descriptor Field Definitions Field Description Ssize Srio Functional Description TXQUEUECNTL0 Address Offset 7E0h TXQUEUECNTL1 Address Offset 7E4hTXQUEUECNTL2 Address Offset 7E8h TXQUEUECNTL3 Address Offset 7ECh TXQUEUECNTL13-0 TXQUEUECNTL17-4TXQUEUECNTL111-8 TXQUEUECNTL23-0 TXQUEUECNTL311-8 TXQUEUECNTL33-0TXQUEUECNTL37-4 Reset and Power Down State TX Operation Message Passing Software RequirementsRX Operation RX Buffer Descriptor Initialization ExampleQueue Mapping RX Buffer Descriptors TX Buffer Descriptor Doorbell Operation MaintenanceStart Message Passing Examples of Doorbellinfo Designations See Figure Info Field SegmentsReg # Bit LSUnREG5 Atomic Operations Congestion Control Detailed Description Flowcntlid FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0 Endianness FL9 Translation for MMR space Endian Conversion TMS320TCI6482 Reset and Power Down Reset HierarchyBus Logical Block Reset and Power Down Summary Enable and Enable Status Registers Global Enable and Global Enable Status Field Descriptions Block Enable and Block Enable Status Field Descriptions EnstatRegisterBit Field Valu Description e Software Shutdown Details EmulationPeripheral Control Register PCR Field Descriptions Peren Soft Free Multiple Ports With 1x Operation Peripheral Control Register PCR Field DescriptionsTX Buffers, Credit, and Packet Reordering Single Port With 1x or 4x Operation Unavailable Outbound Credit 13.2 PLL, Ports, Device ID and Data Rate Initializations Port Mode Register SettingsEnabling the Srio Peripheral Peripheral Initializations Set Device ID Registers Assert the Peren bit to enable logical layer data flow Bootload CapabilityConfiguration and Operation Read register to check portx1-4 OK bit RX Multicast Support Bootload Data MovementDevice Wakeup Multicast DeviceID Operation Daisy Chain Operation and Packet ForwardingEnabling Multicast and Packet Forwarding 16BITDEVIDUPBOUND 16BITDEVIDLOWBOUND Outbound Port8BITDEVIDUPBOUND 8BITDEVIDLOWBOUND For an LSU or the TXU For the MAU or the RXU Msgreqtimeout PktrspnstimeoutRxiodmaaccess Unsolicitedrspns CPU Interrupts General Description Interrupt Condition Status and Clear Registers Interrupt Condition Status and Clear Bits Doorbell Interrupt Condition Status and Clear Registers Doorbell 2 Interrupt Condition Status and Clear Registers Cppi Interrupt Condition Status and Clear Registers RX Cppi Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status and Clear Registers Bit Associated LSU Interrupt Condition LSU4LSU3 LSU2 ICS11 ICS10 ICS9 ICS8 ICS2 ICS1 ICS0ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0 1st Step Nd Step 3rd Step Interrupt Clearing Sequence for Special Event InterruptsInterrupt Function Interrupt Condition Routing Registers Interrupt Condition Routing OptionsDoorbell Interrupt Condition Routing Registers Interrupt Function St Step Nd Step Rd Step Cppi Interrupt Condition Routing Registers ICR7 ICR6 ICR5 ICR4ICR3 ICR2 ICR1 ICR0 ICR15 ICR14 ICR13 ICR12 TX Cppi Interrupt Condition Routing Registers LSU Interrupt Condition Routing Registers ICR23 ICR22 ICR21 ICR20 ICR19 ICR18 ICR17 ICR16ICR31 ICR30 ICR29 ICR28 ICR27 ICR26 ICR25 ICR24 Interrupt Status Decode Registers ICR2 ICR1 ICR0 Interrupt Status Decode Register INTDSTnDECODE Interrupt Generation Interrupt Pacing Interrupt Handling INTDSTnRATECNTL Interrupt Rate Control Register 101 Offset Acronym Register Description IntroductionSerial RapidIO Srio Registers Serial RapidIO Srio Registers Offset Acronym Register Description INTDST3DECODE INTDST4DECODEINTDST5DECODE INTDST6DECODE QUEUE1TXDMAHDP QUEUE15RXDMAHDP QUEUE0RXDMACPQUEUE1RXDMACP QUEUE2RXDMACP RXUMAPL7 RXUMAPH7RXUMAPL8 RXUMAPH8 RXUMAPL30 RXUMAPH30RXUMAPL31 RXUMAPH31 SP1CTL Spipdiscoverytimer SP0SILENCETIMERSP1SILENCETIMER SP2SILENCETIMER Peripheral Identification Register PID Peripheral ID Register PID Field DescriptionsType Class REV Peripheral Control Register PCR Halts Peripheral Settings Control Register Persetcntl Prescalerselect Enable Serdes PLL Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Status Register Gblenstat MMRs for the Srio peripheral Block n Enable Register BLKnEN Block n Enable Registers and the Associated BlocksBlock n Enable Register BLKnEN Field Descriptions Register Address Offset Associated Block Block n Enable Status Register BLKnENSTAT Block n Enable Status Registers and the Associated Blocks RapidIO DEVICEID1 Register DEVICEIDREG1 RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions8BNODEID 16BNODEID RapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions PF16BCNTL Registers Register Address Offset Packet Forwarding Register n for 8-Bit Device IDs PF8BCNTLn PF8BCNTL Registers SERDESCFGRXnCNTL Registers and the Associated Ports Register Address Offset Associated Port Via a 50 pF capacitor to Vssa 127 Swing Invpair Rate Buswidth Entx SERDESCFGTXnCNTL Registers and the Associated PortsSERDESCFGTX3CNTL 129 Serdes Macro Configuration Register n SERDESCFGnCNTL SERDESCFGnCNTL Registers and the Associated Ports 131 DOORBELLn Interrupt Condition Status Register DOORBELLnICSR Doorbell nICSR Registers DOORBELLn Interrupt Condition Clear Register DOORBELLnICCR Doorbell nICCR Registers RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr LSU Interrupt Condition Status Register Lsuicsr ICS31 139 140 LSU Interrupt Condition Clear Register Lsuiccr 31-17 Reserved These reserved bits return 0s when read Errrstevnticcr Field Descriptions Doorbell nICRR Registers Field Value Description = 0 to Eight interrupt destinations INTDST0-INTDST7 146 LSU Interrupt Condition Routing Registers LSUICRR0-LSUICRR3 LSU Interrupt Condition Routing Register Field Descriptions = 0 to 2, 8 to 11, Interrupt destinations INTDST0-INTDST7 Interrupt Status Decode Register INTDSTnDECODE Destination TX buffer descriptor queue 4 bit 4 of Txcppiicsr ∙ Doorbell 0, bit 15 bit 15 of DOORBELL0ICSR ISD1 ISD3ISD2 INTDSTn Interrupt Rate Control Register INTDSTnRATECNTL Countdownvalue LSUn Control Register 0 LSUnREG0 LSUnREG0 Registers and the Associated LSUsLSUn Control Register 0 LSUnREG0 Field Descriptions Addressmsb For packet type 8 maintenance packet LSUn Control Register 1 LSUnREG1LSUnREG1 Registers and the Associated LSUs LSUn Control Register 1 LSUnREG1 Field Descriptions LSUn Control Register 2 LSUnREG2 LSUnREG2 Registers and the Associated LSUsLSUn Control Register 2 LSUnREG2 Field Descriptions Dspaddress LSUn Control Register 3 LSUnREG3 LSUnREG3 Registers and the Associated LSUsLSUn Control Register 3 LSUnREG3 Field Descriptions Bytecount LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 4 LSUnREG4LSUnREG4 Registers and the Associated LSUs LSUn Control Register 5 LSUnREG5 Field Descriptions LSUn Control Register 5 LSUnREG5LSUnREG5 Registers and the Associated LSUs LSUn Control Register 6 LSUnREG6 LSUnREG6 Registers and the Associated LSUsLSUn Control Register 6 LSUnREG6 Field Descriptions Completioncode BSY LSUn Congestion Control Flow Mask Register LSUnFLOWMASKS LSUnFLOWMASKS Registers and the Associated LSUs LSU n supports Flow 8 from table entry QUEUEnTXDMAHDP Registers Register QUEUEnTXDMACP Registers QUEUEnRXDMAHDP Registers QUEUEnRXDMACP Registers Rxcp Transmit Queue Teardown Register Txqueueteardown Txcppiflowmasks Registers and the Associated TX Queues TX Queue n Flowmask Field Descriptions Queue n supports Flow 12 from table entry Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field Descriptions TXQUEUECNTL0 Address Offset 07E0h TXQUEUECNTL1 Address Offset 07E4hTXQUEUECNTL2 Address Offset 07E8h TXQUEUECNTL3 Address Offset 07ECh Field Pair TXQUEUECNTL211-8 Mailbox to Queue Mapping Registers RXUMAPLn and RXUMAPHn 0890h Mapper Lettermask For a single-segment messageFor a multi-segment message Letter Queueid Segmentmapping Flow Control Table Entry Register n FLOWCNTLn Flowcntl n Registers Device Identity CAR Devid Device Identity CAR Devid Field DescriptionsDeviceidentity Devicevendoridentity Deviceidentity Device Information CAR Devinfo Device Information CAR Devinfo Field DescriptionsDevicerev 31-0 Assembly Identity CAR Asblyid Assembly Identity CAR Asblyid Field DescriptionsAssyidentity Assyvendoridentity Assyidentity Assembly Information CAR Asblyinfo Assembly Information CAR Asblyinfo Field DescriptionsExtendedfeaturesptr Assyrev Processing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field Descriptions Source and target of an operation. All PEs shall at minimum Source Operations CAR Srcop Source Operations CAR Srcop Field Descriptions Destination Operations CAR Destop Destination Operations CAR Destop Field DescriptionsRead Write Streamwrite Writewith Datamess Doorbell Resp Andswap Atomic Extendedaddressingcontrol Processing Element Logical Layer Control CSR PellctlAddressing Bit Field Value Local Configuration Space Base Address 0 CSR LclcfghbarLcsba Local Configuration Space Base Address 1 CSR Lclcfgbar Base Device ID CSR Baseid Base Device ID CSR Baseid Field DescriptionsBasedeviceid Largebasedeviceid Host Base Device ID Lock CSR Hostbaseidlock Hostbasedeviceid Componenttag Component Tag CSR ComptagComponent Tag CSR Comptag Field Descriptions Efptr Efid Efptr Port Link Time-Out Control CSR Spltctl Port Link Timeout Control CSR Spltctl Field DescriptionsTimeoutvalue Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Port General Control CSR Spgenctl Field Descriptions Port Link Maintenance Request CSR n SPnLMREQ CommandSPnLMREQ Registers and the Associated Ports SP2LMREQ Port Link Maintenance Response CSR n SPnLMRESP SPnLMRESP Registers and the Associated Ports Port Local AckID Status CSR n SPnACKIDSTAT SPnACKIDSTAT Registers and the Associated Ports SPnERRSTAT Registers and the Associated Ports Port Error and Status CSR n SPnERRSTATPort Error and Status CSR n SPnERRSTAT Field Descriptions Outputerrorenc OutputerrorstpInputerrorenc Inputerrorstp Portok Portuninitialized Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SPnCTLSPnCTL Registers and the Associated Ports Portdisable OutputportenableInputportenable Errorcheckdisable Rather than a parallel port Error Reporting Block Header Register Errrptbh Logical/Transport Layer Error Detect CSR Errdet RX I/O DMA access error Logical/Transport Layer Error Enable CSR Erren Pktresptimeoutenable UnsolicitedrespenableUnsupportedtransenable Rxcppisecurityenable Logical/Transport Layer High Address Capture CSR Haddrcapt ADDRESS6332 Xamsbs Logical/Transport Layer Address Capture CSR AddrcaptADDRESS313 Logical/Transport Layer Device ID Capture CSR Idcapt Msbdestid DestidMsbsourceid Sourceid Msbdestid Logical/Transport Layer Control Capture CSR Ctrlcapt Ftype Ttype MsginfoImpspecific Ftype Port-Write Target Device ID CSR Pwtgtid Port-Write Target Device ID CSR Pwtgtid Field DescriptionsDeviceidmsb Deviceid SPnERRDET Registers and the Associated Ports Port Error Detect CSR n SPnERRDETPort Error Detect CSR n SPnERRDET Field Descriptions Protocolerror DelineationerrorLinktimeout Rcvdpktnotaccpt SPnRATEEN Registers and the Associated Ports Port Error Rate Enable CSR n SPnRATEENPort Error Rate Enable CSR n SPnRATEEN Field Descriptions Protocolerroren DelineationerrorenLinktimeouten Pktunexpectedackiden Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 SPnERRATTRCAPTDBG0 Registers and the Associated Ports Port n Error Capture CSR 1 SPnERRCAPTDBG1 Description Case of a control-symbol errorCase of a packet error SPnERRCAPTDBG1 Registers and the Associated Ports Port n Error Capture CSR 2 SPnERRCAPTDBG2 SPnERRCAPTDBG2 Registers and the Associated Ports Port n Error Capture CSR 3 SPnERRCAPTDBG3 SPnERRCAPTDBG3 Registers and the Associated Ports Port n Error Capture CSR 4 SPnERRCAPTDBG4 SPnERRCAPTDBG4 Registers and the Associated Ports SPnERRRATE Registers and the Associated Ports Port Error Rate CSR n SPnERRRATEPort Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate Threshold CSR n SPnERRTHRESH SPnERRTHRESH Registers and the Associated Ports Discoverytimer Pwtimer Port IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field Descriptions Rsten RstcsPwen Pwirq Prescale Port IP Prescaler Register IpprescalPort IP Prescaler Register Ipprescal Field Descriptions Port-Write-In Capture CSRs SPIPPWINCAPT0-3 Port-Write-In Capture CSR Field Descriptions Port Reset Option CSR n SPnRSTOPT Port Reset Option CSR n SPnRSTOPT Field DescriptionsSPnRSTOPT Registers and the Associated Ports Portid Port Control Independent Register n SPnCTLINDEP SPnCTLINDEP Registers and the Associated Ports Senddbgpkt IlltransenIlltranserr Maxretryen Silencetimer Port Silence Timer n Register SPnSILENCETIMERSPnSILENCETIMER Registers and the Associated Ports Bit Field Value Description 31-0 SPnMULTEVNTCS Registers and the Associated PortsMultevntcs Port Control Symbol Transmit n Register SPnCSTX SPnCSTX Registers and the Associated PortsSTYPE0 PAR0 PAR1 STYPE1 CMD Csemb STYPE0 Index Comptag Ctrlcapt Devinfo Pellctl Haddrcapt Lsuicsr 237 Pefeat 232 Srio Registers Rxcppicntl Rxcppiiccr Rxcppiicrr RXCPPIICRR2 Rxcppiicsr Broken link Degraded link Maximum retry error at port n Txqueueteardown Xoff Xon Important Notice