![](/images/new-backgrounds/1192952/192952393x1.webp)
www.ti.com
SRIO Registers
5.66 Port Link Time-Out Control CSR (SP_LT_CTL)
The port link
Figure 129. Port Link Time-Out Control CSR (SP_LT_CTL) - Address Offset 1120h
31
TIMEOUT_VALUE
8 | 7 | 0 |
TIMEOUT_VALUE |
| Reserved |
|
LEGEND: R/W = Read/Write; R = Read only;
Table 137. Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions
Bit | Field | Value | Description |
TIMEOUT_VALUE |
| Timeout value for all ports on the device. This timeout is for link events | |
|
|
| such as sending a packet to receiving the corresponding ACK. Max |
|
|
| value represents |
|
|
| Value; where Timeout value is the decimal representation of this register |
|
|
| value. |
|
| FFFFFFh | 3.4 s |
|
| 0FFFFFh | 215 ms |
|
| 00FFFFh | 13.4 ms |
|
| 000FFFh | 839.5 μs |
|
| 0000FFh | 52.3 μs |
|
| 00000Fh | 3.1 μs |
|
| 000001h | 205 ns for simulation only |
|
| 000000h | Timer disabled |
Reserved | 00h | These |
SPRUE13A | Serial RapidIO (SRIO) | 197 |
Submit Documentation Feedback |
|
|