SRIO Registers

 

for doorbell interrupt conditions 144

for error, reset, and special event (port) interrupt

conditions 149

 

for LSU interrupt conditions

147

RST_CS field of SP_IP_MODE

231

RST_EN field of SP_IP_MODE

231

rules for CPPI data traffic 43

 

RX_CP field of QUEUEn_RXDMA_CP 167

RX_CPPI_CNTL 173

 

RX_CPPI_ICCR 135

 

RX_CPPI_ICRR 145

 

RX_CPPI_ICRR2 145

 

RX_CPPI_ICSR 134

 

RX_CPPI_SECURITY_ENABLE field of ERR_EN 212

RX_CPPI_SECURITY field of ERR_DET

210

RX_HDP field of QUEUEn_RXDMA_HDP

166

RX_IO_DMA_ACCESS field of ERR_DET

210

RX_IO_SECURITY_ENABLE field of ERR_EN 212

RX_QUEUE_TEAR_DOWN 172

 

 

RX buffer descriptor fields 47

 

 

RX buffer descriptor link-list figure 61

 

RX buffer descriptor queue teardown

50

 

RX CPPI security error

 

 

reporting enable field 213

 

 

status bit 211

 

 

RX I/O DMA access error

 

 

reporting enable field 213

 

 

status field

211

 

 

RX shared buffer

 

 

in direct I/O RX operation 42

 

 

in direct I/O TX READ transaction

41

 

in SRIO component block diagram

26

 

RXU

 

 

 

enable bit

119

 

 

enable status bits 117, 120

 

 

handling of unavailable outbound credit

76

in SRIO component block diagram

26

 

RXU_MAP registers

 

 

description

177

 

 

introduction

45

 

 

S

security error reporting enable bit for MAU

213

security error reporting enable bit for RXU

213

security error status bit for MAU

211

 

 

 

security error status bit for RXU

211

 

 

 

SEGMENT_MAPPING field of RXU_MAP_Hn

178

segmentation of outbound direct I/O requests

42

SELF_RST field of SP_IP_MODE 231

 

 

 

self reset interrupt enable field for ports

231

 

SEND_DBG_PKT field of SPn_CTL_INDEP

 

236

send debug packet field for port n 237

 

 

 

SERDES_CFGn_CNTL 130

 

 

 

 

SERDES_CFGRXn_CNTL 125

 

 

 

 

SERDES_CFGTXn_CNTL 128

 

 

 

 

SERDES macro configuration register

130

 

 

252

Index

SERDES macros

 

 

 

 

configuration example 35

 

 

 

 

description

28

 

 

 

 

enable bits

115

 

 

 

 

in SRIO component block diagram

26

 

in SRIO peripheral block diagram

21

 

PLL enabling 28

 

 

 

 

receiver enabling 30

 

 

 

 

transmitter enabling 33

 

 

 

 

SERDES receive channel configuration registers

125

SERDES transmit channel configuration registers

128

serialization/deserialization (SERDES) 21

 

serial port IP prescaler register

233

 

 

Serial RapidIO peripheral. See SRIO peripheral

19

shared buffers

 

 

 

 

in direct I/O RX operation 42

 

 

 

in direct I/O TX READ transaction

41

 

in direct I/O TX WRITE transaction

40

 

in Load/Store module data flow diagram 39

 

in message passing 43

 

 

 

 

in SRIO component block diagram

26

 

SILENCE_TIMER field of SPn_SILENCE_TIMER

238

silent state period for port n 238

 

 

 

single-/multi-segment selection field for message

 

reception

180

 

 

 

 

single port with 1x or 4x operation

76

 

small common transport system base device ID

193

SOFT_REC field of SPn_CTL_INDEP 236

 

SOFT field of PCR 112

 

 

 

 

soft stop bit

112

 

 

 

 

soft stop emulation mode 75

 

 

 

 

software memory sleep override bit

 

113

 

software requirements for message passing 60

 

software shutdown details 74

 

 

 

 

sop field of RX buffer descriptor

47

 

 

sop field of TX buffer descriptor

52

 

 

source address field for LSUn

157

 

 

source ID associated with logical/transport error

216

source ID check or ignore field for message reception

180

 

 

 

 

 

SOURCEID field of ID_CAPT 216

 

 

 

SOURCEID field of RXU_MAP_Ln

178

 

source operations CAR 188

 

 

 

 

SP_GEN_CTL 199

 

 

 

 

SP_IP_DISCOVERY_TIMER 230

 

 

 

SP_IP_IPW_IN_CAPTn 234

 

 

 

 

SP_IP_MODE 231

 

 

 

 

SP_LT_CTL 197

 

 

 

 

SP_MB_HEAD 196

 

 

 

 

SP_MODE field of SP_IP_MODE

231

 

SP_RT_CTL 198

 

 

 

 

SPn_ACKID_STAT 202

 

 

 

 

SPn_CS_TX

240

 

 

 

 

SPn_CTL 206

SPn_CTL_INDEP 236

SPn_ERR_ATTR_CAPT_DBG0 223

SPRUE13A –September 2006

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