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SRIO Functional Description
Table 5. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL) Field Descriptions
Bit | Field | Value | Description |
Reserved | 0000h | Reserved | |
LB |
| Loop bandwidth. Specify loop bandwidth settings. Jitter on the reference clock will | |
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| degrade both the transmit eye and receiver jitter tolerance thereby impairing system |
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| performance. Performance of the integrated PLL can be optimized according to the |
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| jitter characteristics of the reference clock via the LB field. |
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| 00b | Frequency dependent bandwidth. The PLL bandwidth is set to a twelfth of the |
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| frequency of RIOCLK/RIOCLK. This setting is suitable for most systems that input the |
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| reference clock via a low jitter input cell, and is required for standards compliance |
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| 01b | Reserved |
|
| 10b | Low bandwidth. The PLL bandwidth is set to a twentieth of the frequency of |
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| RIOCLK/RIOCLK, or 3MHz (whichever is larger). In systems where the reference |
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| clock is directly input via a low jitter input cell, but is of lower quality, this setting may |
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| offer better performance. It will reduce the amount of reference clock jitter transferred |
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| through the PLL. However, it also increases the susceptibility to loop noise generated |
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| within the PLL itself. It is difficult to predict whether the improvement in the former will |
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| more than offset the degradation in the latter. |
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| 11b | High bandwidth. The PLL bandwidth is set to a eighth of the frequency of |
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| RIOCLK/RIOCLK. This is the setting appropriate for systems where the reference |
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| clock is cleaned through an ultra low jitter |
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| be achieved even if the reference clock input to the cleaner PLL is outside the |
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| specification for the standard. |
Reserved | 00h | Reserved | |
MPY |
| PLL multiply. Select PLL multiply factors between 4 and 60. | |
|
| 00000b | 4x |
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| 00001b | 5x |
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| 00010b | 6x |
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| 00011b | Reserved |
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| 00100b | 8x |
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| 00101b | 10x |
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| 00110b | 12x |
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| 00111b | 12.5x |
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| 01000b | 15x |
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| 01001b | 20x |
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| 01010b | 25x |
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| 01011b | Reserved |
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| 01100b | Reserved |
|
| 01111b | Reserved |
|
| 1xxxxb | Reserved |
0 | ENPLL |
| Enable PLL |
|
| 0 | PLL disabled |
|
| 1 | PLL enabled |
Based on the MPY value, the line rate versus PLL output clock frequency can be calculated. This is summarized in Table 6.
SPRUE13A | Serial RapidIO (SRIO) | 29 |