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SRIO Registers
5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)
The bits in this register indicate any active interrupt requests from TX buffer descriptor queues. TX_CPPI_ICSR is shown in Figure 81 and described in Table 71.
Figure 81. TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250h
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| 16 |
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| Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ICS15 | ICS14 | ICS13 | ICS12 | ICS11 | ICS10 | ICS9 | ICS8 | ICS7 | ICS6 | ICS5 | ICS4 | ICS3 | ICS2 | ICS1 | ICS0 |
LEGEND: R/W = Read/Write; R = Read only;
Table 71. TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) Field Descriptions
Bit | Field |
Reserved | |
ICSx | |
| (x = 15 to 0) |
Value
Description
0 These
0 TX buffer descriptor queue x has not generated an interrupt request.
1 TX buffer descriptor queue x has generated an interrupt request.
136 | Serial RapidIO (SRIO) | SPRUE13A |
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