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Texas Instruments TMS320TCI648x manual LSU Interrupt Condition Clear Register Lsuiccr

Models: TMS320TCI648x

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SRIO Registers

5.23 LSU Interrupt Condition Clear Register (LSU_ICCR)

Setting a bit in this register clears the corresponding bit in LSU_ICSR, to acknowledge the interrupt.

LSU_ICCR is shown in Figure 84 and described in Table 74. For additional programming information, see Section 4.3.3.

Figure 84. LSU Interrupt Condition Clear Register (LSU_ICCR) - Address Offset 0268h

<---------------------------------

Bits for LSU4 ---------------------------------

>

<---------------------------------

Bits for LSU3 ---------------------------------

>

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

ICC31

ICC30

ICC29

ICC28

ICC27

ICC26

ICC25

ICC24

ICC23

ICC22

ICC21

ICC20

ICC19

ICC18

ICC17

ICC16

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

<---------------------------------

Bits for LSU2 ---------------------------------

>

<---------------------------------

Bits for LSU1 ---------------------------------

>

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ICC15

ICC14

ICC13

ICC12

ICC11

ICC10

ICC9

ICC8

ICC7

ICC6

ICC5

ICC4

ICC3

ICC2

ICC1

ICC0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

LEGEND: W = Write only; -n= Value after reset

Table 74. LSU Interrupt Condition Clear Register (LSU_ICCR) Field Descriptions

Bit	Field	Value	Description
31–0	ICCx	0	No effect
	(x = 31 to 0)	1	Clear bit x of the LSU interrupt condition status register (LSU_ICSR).
		1

SPRUE13A –September 2006	Serial RapidIO (SRIO)	141
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Texas Instruments TMS320TCI648x manual LSU Interrupt Condition Clear Register Lsuiccr

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticsr Port Link Maintenance Request CSR n SP n Lmreq List of Figures INTDSTnRATECNTL Interrupt Rate Control Register Transmit Cppi Supported Flow Mask Registers Port-Write-In Capture CSRs List of Tables PF16BCNTL Registers LSUnREG6 Registers and the Associated LSUs SP n Errdet Registers and the Associated Ports Read This First Trademarks RapidIO Architectural Hierarchy General RapidIO SystemOverview RapidIO Interconnect Architecture Physical Layer 1x/4x LP-Serial SpecificationFeatures Supported in Srio Peripheral RapidIO Feature Support in SrioStandards External Devices Requirements Features Not SupportedTI Devices Supported By This Document TI Devices Supported By This DocumentPeripheral Data Flow OverviewRegisters Checked for Multicast DeviceID Registers Checked For Multicast DeviceIDOperation Sequence Srio PacketsExample Packet Streaming Write Operation Sequence4x RapidIO Packet Data Stream Streaming-Write Class Control SymbolsSrio Packet Type Srio PinsPacket Types Ftype Ttype Packet TypeComponent Block Diagram Functional OperationPin Description Srio Component Block Diagram Serdes Macro and its Configurations Enabling the PLLMPY Enpll MPY Bit Field Value DescriptionEffect of the Rate Bits Line Rate versus PLL Output Clock FrequencyFrequency Range versus MPY Value Enabling the ReceiverCDR LOS Align Term Invpair Rate Buswidth EnrxBit Field LOS EQ Bits Enabling the TransmitterCFGRX22-19 Swing DE Bits of SERDESCFGTXnCNTLAmplitude Reduction DE BitsSwing Bits of SERDESCFGTXnCNTL Serdes Configuration ExampleDirect I/O Operation Swing BitsLSU Register Field RapidIO Packet Header Field LSU Control/Command Register FieldsLSU Status Register Fields LSU Register Field FunctionBSY LSU Registers Timing Detailed Data Path Description Example Burst NwriterWrite Transactions Direct I/O TX OperationRead Transactions Direct I/O RX Operation SegmentationMessage Passing Reset and Power Down StateCppi RX Scheme for RapidIO RX OperationMessage Request Packet Mailbox to Queue Mapping Register L n Rxumapl n RX DMA State Completion Pointer CP Address Offset 680h-6BChMailbox to Queue Mapping Register H n Rxumaph n Bit Name DescriptionField Description RX Buffer Descriptor Field DescriptionsDSP core uses this bit to reclaim buffers RX Cppi Mode Explanation Srio Functional Description TX Operation Cppi Boundary DiagramTX Buffer Descriptor Field Definitions TX DMA State Completion Pointer CP Address Offset 58h-5BChField Description TX Buffer Descriptor Field DefinitionsSsize Srio Functional Description TXQUEUECNTL1 Address Offset 7E4h TXQUEUECNTL0 Address Offset 7E0hTXQUEUECNTL2 Address Offset 7E8h TXQUEUECNTL3 Address Offset 7EChTXQUEUECNTL17-4 TXQUEUECNTL13-0TXQUEUECNTL111-8 TXQUEUECNTL23-0TXQUEUECNTL33-0 TXQUEUECNTL37-4TXQUEUECNTL311-8 Reset and Power Down State Message Passing Software Requirements RX OperationTX Operation Initialization Example Queue MappingRX Buffer Descriptor TX Buffer Descriptor RX Buffer DescriptorsMaintenance Start Message PassingDoorbell Operation Info Field Segments Examples of Doorbellinfo Designations See FigureReg # Bit LSUnREG5Congestion Control Atomic OperationsDetailed Description FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0 FlowcntlidFL9 EndiannessEndian Conversion TMS320TCI6482 Translation for MMR spaceReset Hierarchy Reset and Power DownBus Logical BlockEnable and Enable Status Registers Reset and Power Down SummaryGlobal Enable and Global Enable Status Field Descriptions Enstat Block Enable and Block Enable Status Field DescriptionsRegisterBit Field Valu Description eEmulation Software Shutdown DetailsPeripheral Control Register PCR Field Descriptions Peren Soft FreePeripheral Control Register PCR Field Descriptions TX Buffers, Credit, and Packet ReorderingMultiple Ports With 1x Operation Unavailable Outbound Credit Single Port With 1x or 4x OperationPort Mode Register Settings Enabling the Srio Peripheral13.2 PLL, Ports, Device ID and Data Rate Initializations Set Device ID Registers Peripheral InitializationsBootload Capability Assert the Peren bit to enable logical layer data flowConfiguration and Operation Read register to check portx1-4 OK bitBootload Data Movement Device WakeupRX Multicast Support Daisy Chain Operation and Packet Forwarding Multicast DeviceID OperationEnabling Multicast and Packet Forwarding 16BITDEVIDUPBOUND 16BITDEVIDLOWBOUNDPort Outbound8BITDEVIDUPBOUND 8BITDEVIDLOWBOUNDFor the MAU or the RXU For an LSU or the TXUPktrspnstimeout MsgreqtimeoutRxiodmaaccess UnsolicitedrspnsGeneral Description CPU InterruptsInterrupt Condition Status and Clear Registers Doorbell Interrupt Condition Status and Clear Registers Interrupt Condition Status and Clear BitsCppi Interrupt Condition Status and Clear Registers Doorbell 2 Interrupt Condition Status and Clear RegistersLSU Interrupt Condition Status and Clear Registers RX Cppi Interrupt Condition Status and Clear RegistersLSU4 Bit Associated LSU Interrupt ConditionLSU3 LSU2ICS2 ICS1 ICS0 ICS11 ICS10 ICS9 ICS8ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0Interrupt Clearing Sequence for Special Event Interrupts Interrupt Function1st Step Nd Step 3rd Step Interrupt Condition Routing Options Interrupt Condition Routing RegistersDoorbell Interrupt Condition Routing Registers Interrupt Function St Step Nd Step Rd StepICR7 ICR6 ICR5 ICR4 Cppi Interrupt Condition Routing RegistersICR3 ICR2 ICR1 ICR0 ICR15 ICR14 ICR13 ICR12LSU Interrupt Condition Routing Registers TX Cppi Interrupt Condition Routing RegistersICR19 ICR18 ICR17 ICR16 ICR23 ICR22 ICR21 ICR20ICR31 ICR30 ICR29 ICR28 ICR27 ICR26 ICR25 ICR24ICR2 ICR1 ICR0 Interrupt Status Decode RegistersInterrupt Status Decode Register INTDSTnDECODE Interrupt Pacing Interrupt GenerationINTDSTnRATECNTL Interrupt Rate Control Register Interrupt Handling101 Introduction Serial RapidIO Srio RegistersOffset Acronym Register Description Offset Acronym Register Description Serial RapidIO Srio RegistersINTDST4DECODE INTDST3DECODEINTDST5DECODE INTDST6DECODEQUEUE1TXDMAHDP QUEUE0RXDMACP QUEUE15RXDMAHDPQUEUE1RXDMACP QUEUE2RXDMACPRXUMAPH7 RXUMAPL7RXUMAPL8 RXUMAPH8RXUMAPH30 RXUMAPL30RXUMAPL31 RXUMAPH31SP1CTL SP0SILENCETIMER SpipdiscoverytimerSP1SILENCETIMER SP2SILENCETIMERPeripheral ID Register PID Field Descriptions Peripheral Identification Register PIDType Class REVHalts Peripheral Control Register PCRPeripheral Settings Control Register Persetcntl Prescalerselect Enable Serdes PLL Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Register GblenPeripheral Global Enable Status Register Gblenstat MMRs for the Srio peripheral Block n Enable Registers and the Associated Blocks Block n Enable Register BLKnENBlock n Enable Register BLKnEN Field Descriptions Register Address Offset Associated BlockBlock n Enable Status Registers and the Associated Blocks Block n Enable Status Register BLKnENSTATRapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions RapidIO DEVICEID1 Register DEVICEIDREG18BNODEID 16BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions RapidIO DEVICEID2 Register DEVICEIDREG2Register Address Offset PF16BCNTL RegistersPF8BCNTL Registers Packet Forwarding Register n for 8-Bit Device IDs PF8BCNTLnRegister Address Offset Associated Port SERDESCFGRXnCNTL Registers and the Associated PortsVia a 50 pF capacitor to Vssa 127 SERDESCFGTXnCNTL Registers and the Associated Ports SERDESCFGTX3CNTLSwing Invpair Rate Buswidth Entx 129 SERDESCFGnCNTL Registers and the Associated Ports Serdes Macro Configuration Register n SERDESCFGnCNTL131 Doorbell nICSR Registers DOORBELLn Interrupt Condition Status Register DOORBELLnICSRDoorbell nICCR Registers DOORBELLn Interrupt Condition Clear Register DOORBELLnICCRRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr ICS31 LSU Interrupt Condition Status Register Lsuicsr139 140 LSU Interrupt Condition Clear Register Lsuiccr 31-17 Reserved These reserved bits return 0s when read Errrstevnticcr Field Descriptions Field Value Description Doorbell nICRR Registers= 0 to Eight interrupt destinations INTDST0-INTDST7 146 LSU Interrupt Condition Routing Registers LSUICRR0-LSUICRR3 LSU Interrupt Condition Routing Register Field Descriptions = 0 to 2, 8 to 11, Interrupt destinations INTDST0-INTDST7 Destination Interrupt Status Decode Register INTDSTnDECODETX buffer descriptor queue 4 bit 4 of Txcppiicsr ∙ Doorbell 0, bit 15 bit 15 of DOORBELL0ICSR ISD3 ISD2ISD1 Countdownvalue INTDSTn Interrupt Rate Control Register INTDSTnRATECNTLLSUnREG0 Registers and the Associated LSUs LSUn Control Register 0 LSUnREG0LSUn Control Register 0 LSUnREG0 Field Descriptions AddressmsbLSUn Control Register 1 LSUnREG1 For packet type 8 maintenance packetLSUnREG1 Registers and the Associated LSUs LSUn Control Register 1 LSUnREG1 Field DescriptionsLSUnREG2 Registers and the Associated LSUs LSUn Control Register 2 LSUnREG2LSUn Control Register 2 LSUnREG2 Field Descriptions DspaddressLSUnREG3 Registers and the Associated LSUs LSUn Control Register 3 LSUnREG3LSUn Control Register 3 LSUnREG3 Field Descriptions BytecountLSUn Control Register 4 LSUnREG4 LSUnREG4 Registers and the Associated LSUsLSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 5 LSUnREG5 LSUnREG5 Registers and the Associated LSUsLSUn Control Register 5 LSUnREG5 Field Descriptions LSUnREG6 Registers and the Associated LSUs LSUn Control Register 6 LSUnREG6LSUn Control Register 6 LSUnREG6 Field Descriptions Completioncode BSYLSUnFLOWMASKS Registers and the Associated LSUs LSUn Congestion Control Flow Mask Register LSUnFLOWMASKSLSU n supports Flow 8 from table entry Register QUEUEnTXDMAHDP RegistersQUEUEnTXDMACP Registers QUEUEnRXDMAHDP Registers Rxcp QUEUEnRXDMACP RegistersTransmit Queue Teardown Register Txqueueteardown Txcppiflowmasks Registers and the Associated TX Queues TX Queue n Flowmask Field Descriptions Queue n supports Flow 12 from table entry Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Field Descriptions Receive Cppi Control Register RxcppicntlTXQUEUECNTL1 Address Offset 07E4h TXQUEUECNTL0 Address Offset 07E0hTXQUEUECNTL2 Address Offset 07E8h TXQUEUECNTL3 Address Offset 07EChField Pair TXQUEUECNTL211-8 Mailbox to Queue Mapping Registers RXUMAPLn and RXUMAPHn 0890h Mapper For a single-segment message LettermaskFor a multi-segment message LetterSegmentmapping QueueidFlowcntl n Registers Flow Control Table Entry Register n FLOWCNTLnDevice Identity CAR Devid Field Descriptions Device Identity CAR DevidDeviceidentity Devicevendoridentity DeviceidentityDevice Information CAR Devinfo Field Descriptions Device Information CAR DevinfoDevicerev 31-0Assembly Identity CAR Asblyid Field Descriptions Assembly Identity CAR AsblyidAssyidentity Assyvendoridentity AssyidentityAssembly Information CAR Asblyinfo Field Descriptions Assembly Information CAR AsblyinfoExtendedfeaturesptr AssyrevProcessing Element Features CAR Pefeat Field Descriptions Processing Element Features CAR PefeatSource and target of an operation. All PEs shall at minimum Source Operations CAR Srcop Field Descriptions Source Operations CAR SrcopDestination Operations CAR Destop Field Descriptions Destination Operations CAR DestopRead Write Streamwrite Writewith Datamess Doorbell Resp Andswap AtomicProcessing Element Logical Layer Control CSR Pellctl AddressingExtendedaddressingcontrol Local Configuration Space Base Address 0 CSR Lclcfghbar LcsbaBit Field Value Local Configuration Space Base Address 1 CSR Lclcfgbar Base Device ID CSR Baseid Field Descriptions Base Device ID CSR BaseidBasedeviceid LargebasedeviceidHostbasedeviceid Host Base Device ID Lock CSR HostbaseidlockComponent Tag CSR Comptag Component Tag CSR Comptag Field DescriptionsComponenttag Efptr Efptr EfidPort Link Timeout Control CSR Spltctl Field Descriptions TimeoutvaluePort Link Time-Out Control CSR Spltctl Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Field Descriptions Port General Control CSR SpgenctlCommand Port Link Maintenance Request CSR n SPnLMREQSPnLMREQ Registers and the Associated Ports SP2LMREQSPnLMRESP Registers and the Associated Ports Port Link Maintenance Response CSR n SPnLMRESPSPnACKIDSTAT Registers and the Associated Ports Port Local AckID Status CSR n SPnACKIDSTATPort Error and Status CSR n SPnERRSTAT Port Error and Status CSR n SPnERRSTAT Field DescriptionsSPnERRSTAT Registers and the Associated Ports Outputerrorstp OutputerrorencInputerrorenc InputerrorstpPortuninitialized PortokPort Control CSR n SPnCTL SPnCTL Registers and the Associated PortsPort Control CSR n SPnCTL Field Descriptions Outputportenable PortdisableInputportenable ErrorcheckdisableRather than a parallel port Error Reporting Block Header Register Errrptbh Logical/Transport Layer Error Detect CSR Errdet RX I/O DMA access error Logical/Transport Layer Error Enable CSR Erren Unsolicitedrespenable PktresptimeoutenableUnsupportedtransenable RxcppisecurityenableADDRESS6332 Logical/Transport Layer High Address Capture CSR HaddrcaptLogical/Transport Layer Address Capture CSR Addrcapt ADDRESS313Xamsbs Msbdestid Destid Logical/Transport Layer Device ID Capture CSR IdcaptMsbsourceid Sourceid MsbdestidFtype Ttype Msginfo Logical/Transport Layer Control Capture CSR CtrlcaptImpspecific FtypePort-Write Target Device ID CSR Pwtgtid Field Descriptions Port-Write Target Device ID CSR PwtgtidDeviceidmsb DeviceidPort Error Detect CSR n SPnERRDET Port Error Detect CSR n SPnERRDET Field DescriptionsSPnERRDET Registers and the Associated Ports Delineationerror ProtocolerrorLinktimeout RcvdpktnotaccptPort Error Rate Enable CSR n SPnRATEEN Port Error Rate Enable CSR n SPnRATEEN Field DescriptionsSPnRATEEN Registers and the Associated Ports Delineationerroren ProtocolerrorenLinktimeouten PktunexpectedackidenSPnERRATTRCAPTDBG0 Registers and the Associated Ports Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0Description Case of a control-symbol error Port n Error Capture CSR 1 SPnERRCAPTDBG1Case of a packet error SPnERRCAPTDBG1 Registers and the Associated PortsSPnERRCAPTDBG2 Registers and the Associated Ports Port n Error Capture CSR 2 SPnERRCAPTDBG2SPnERRCAPTDBG3 Registers and the Associated Ports Port n Error Capture CSR 3 SPnERRCAPTDBG3SPnERRCAPTDBG4 Registers and the Associated Ports Port n Error Capture CSR 4 SPnERRCAPTDBG4Port Error Rate CSR n SPnERRRATE Port Error Rate CSR n SPnERRRATE Field DescriptionsSPnERRRATE Registers and the Associated Ports SPnERRTHRESH Registers and the Associated Ports Port Error Rate Threshold CSR n SPnERRTHRESHPwtimer DiscoverytimerPort IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR SpipmodeRstcs RstenPwen PwirqPort IP Prescaler Register Ipprescal Port IP Prescaler Register Ipprescal Field DescriptionsPrescale Port-Write-In Capture CSR Field Descriptions Port-Write-In Capture CSRs SPIPPWINCAPT0-3Port Reset Option CSR n SPnRSTOPT Field Descriptions Port Reset Option CSR n SPnRSTOPTSPnRSTOPT Registers and the Associated Ports PortidSPnCTLINDEP Registers and the Associated Ports Port Control Independent Register n SPnCTLINDEPIlltransen SenddbgpktIlltranserr MaxretryenPort Silence Timer n Register SPnSILENCETIMER SPnSILENCETIMER Registers and the Associated PortsSilencetimer SPnMULTEVNTCS Registers and the Associated Ports MultevntcsBit Field Value Description 31-0 SPnCSTX Registers and the Associated Ports Port Control Symbol Transmit n Register SPnCSTXSTYPE0 PAR0 PAR1 STYPE1 CMD Csemb STYPE0Index Comptag Ctrlcapt Devinfo Pellctl Haddrcapt Lsuicsr 237 Pefeat 232 Srio Registers Rxcppicntl Rxcppiiccr Rxcppiicrr RXCPPIICRR2 Rxcppiicsr Broken link Degraded link Maximum retry error at port n Txqueueteardown Xoff Xon Important Notice