| 5.23 | LSU Interrupt Condition Clear Register (LSU_ICCR) | 141 |
| 5.24 | Error, Reset, and Special Event Interrupt Condition Status Register |
|
|
| (ERR_RST_EVNT_ICSR) | 142 |
| 5.25 | Error, Reset, and Special Event Interrupt Condition Clear Register |
|
|
| (ERR_RST_EVNT_ICCR) | 143 |
| 5.26 | DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and |
|
|
| DOORBELLn_ICRR2) | 144 |
| 5.27 | RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2) | 145 |
| 5.28 | TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2) | 146 |
| 5.29 | LSU Interrupt Condition Routing Registers | 147 |
| 5.30 | Error, Reset, and Special Event Interrupt Condition Routing Registers |
|
|
| (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3) | 149 |
| 5.31 | Interrupt Status Decode Register (INTDSTn_DECODE) | 150 |
| 5.32 | INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL) | 154 |
| 5.33 | LSUn Control Register 0 (LSUn_REG0) | 155 |
| 5.34 | LSUn Control Register 1 (LSUn_REG1) | 156 |
| 5.35 | LSUn Control Register 2 (LSUn_REG2) | 157 |
| 5.36 | LSUn Control Register 3 (LSUn_REG3) | 158 |
| 5.37 | LSUn Control Register 4 (LSUn_REG4) | 159 |
| 5.38 | LSUn Control Register 5 (LSUn_REG5) | 160 |
| 5.39 | LSUn Control Register 6 (LSUn_REG6) | 161 |
| 5.40 | LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) | 162 |
| 5.41 | Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP) | 164 |
| 5.42 | Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP) | 165 |
| 5.43 | Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP) | 166 |
| 5.44 | Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) | 167 |
| 5.45 | Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) | 168 |
| 5.46 | Transmit CPPI Supported Flow Mask Registers | 169 |
| 5.47 | Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) | 172 |
| 5.48 | Receive CPPI Control Register (RX_CPPI_CNTL) | 173 |
| 5.49 | Transmit CPPI Weighted Round Robin Control Registers | 174 |
| 5.50 | Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn) | 177 |
| 5.51 | Flow Control Table Entry Register n (FLOW_CNTLn) | 181 |
| 5.52 | Device Identity CAR (DEV_ID) | 182 |
| 5.53 | Device Information CAR (DEV_INFO) | 183 |
| 5.54 | Assembly Identity CAR (ASBLY_ID) | 184 |
| 5.55 | Assembly Information CAR (ASBLY_INFO) | 185 |
| 5.56 | Processing Element Features CAR (PE_FEAT) | 186 |
| 5.57 | Source Operations CAR (SRC_OP) | 188 |
| 5.58 | Destination Operations CAR (DEST_OP) | 189 |
| 5.59 | Processing Element Logical Layer Control CSR (PE_LL_CTL) | 190 |
| 5.60 | Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) | 191 |
| 5.61 | Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) | 192 |
| 5.62 | Base Device ID CSR (BASE_ID) | 193 |
| 5.63 | Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK) | 194 |
| 5.64 | Component Tag CSR (COMP_TAG) | 195 |
| 5.65 | 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD) | 196 |
| 5.66 | Port Link | 197 |
| 5.67 | Port Response | 198 |
| 5.68 | Port General Control CSR (SP_GEN_CTL) | 199 |
4 | Contents | SPRUE13A | |
