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Overview
Figure 1. RapidIO Architectural Hierarchy
Logicalspecification
Informationnecessaryfortheendpoint
toprocessthetransaction(i.e.,transaction
type,size,physicaladdress)
I/O
system
Message
passing
Globally
shared
memory
Future logical spec
Transportspecification
Informationtotransportpacketfromend
toendinthesystem(i.e.,routingaddress)
Common transport spec
Physicalspecification
Informationnecessarytomovepacket
betweentwophysicaldevices(i.e.,electrical
interface,flowcontrol)
8/16
LP-LVDS
1x/4x
LP serial
Future
physical
spec
Inter-
operability
specification
Compliance
checklist
SPRUE13A | Serial RapidIO (SRIO) | 17 |