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SRIO Registers
5.44 Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP)
There are sixteen of these registers (see Table 110). QUEUEn_RXDMA_CP is shown in Figure 106 and described in Table 111. For additional programming information, see Section 2.3.4.1 .
Table 110. QUEUEn_RXDMA_CP Registers
Register | Address Offset |
QUEUE0_RXDMA_CP | 0680h |
QUEUE1_RXDMA_CP | 0684h |
QUEUE2_RXDMA_CP | 0688h |
QUEUE3_RXDMA_CP | 068Ch |
QUEUE4_RXDMA_CP | 0690h |
QUEUE5_RXDMA_CP | 0694h |
QUEUE6_RXDMA_CP | 0698h |
QUEUE7_RXDMA_CP | 069Ch |
QUEUE8_RXDMA_CP | 06A0h |
QUEUE9_RXDMA_CP | 06A4h |
QUEUE10_RXDMA_CP | 06A8h |
QUEUE11_RXDMA_CP | 06ACh |
QUEUE12_RXDMA_CP | 06B0h |
QUEUE13_RXDMA_CP | 06B4h |
QUEUE14_RXDMA_CP | 06B8h |
QUEUE15_RXDMA_CP | 06BCh |
Figure 106. Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP)
31 | 0 |
RX_CP
LEGEND: R/W = Read/Write;
Table 111. Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP) Field
Descriptions
Bit | Field | Value | Description |
RX_CP | 00000000h | This field is the memory address for the receive queue completion pointer. This | |
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| to | register is written by the DSP core with the buffer descriptor address for the last |
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| FFFFFFFFh | buffer processed by the DSP core during interrupt processing. The port uses the |
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| value written to determine if the interrupt should be deasserted. |
SPRUE13A | Serial RapidIO (SRIO) | 167 |
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