Texas Instruments TMS320TCI648x manual DE Bits of SERDESCFGTXnCNTL, Swing, Amplitude Reduction

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SRIO Functional Description

Table 11. SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL) Field

Descriptions (continued)

Bit	Field	Value	Description
15–12	DE	0000b–1111b	De-emphasis. Selects one of 15 output de-emphasis settings from 4.76 to 71.42%.
			De-emphasis provides a means to compensate for high frequency attenuation in the
			attached media. It causes the output amplitude to be smaller for bits which are not
			preceded by a transition than for bits which are. See Table 12.
11–9	SWING	000b–111b	Output swing. Selects one of 8 outputs amplitude settings between 125 and
			1250mVdfpp. See Table 13.
8	CM		Common mode. Adjusts the common mode to suit the termination at the attached
			receiver. For output swing settings above 750mV, this reduced common mode can
			cause distortion of the waveform. Under these conditions, this bit should be set high to
			offset some of the common mode reduction.
		0	Normal common mode. Common mode not adjusted.
		1	Raised common mode. Common mode raised by 5% of difference between RIOTXn
			and RIOTXn
7	INVPAIR		Invert polarity. Inverts the polarity of RIOTXn and RIOTXn.
		0	Normal polarity. RIOTXn is considered to be positive data and RIOTXn negative.
		1	Inverted polarity. RIOTXn is considered to be negative data and RIOTXn positive.
6–5	RATE		Operating rate. Selects full, half, or quarter rate operation.
		00b	Full rate. Two data samples taken per PLL output clock cycle.
		01b	Half rate. One data sample taken per PLL output clock cycle.
		10b	Quarter rate. One data sample taken every two PLL output clock cycles.
		11b	Reserved
4–2	BUSWIDTH	000b	Bus width. Always write 000b to this field, to indicate a 10-bit-wide parallel bus to the
			clock. All other values are reserved. See Section 2.3.2.1 for an explanation of the bus.
1	Reserved	0	Always write 0 to this reserved bit.
0	ENTX		Enable transmitter
		0	Disable this transmitter.
		1	Enable this transmitter.

Table 12. DE Bits of SERDES_CFGTXn_CNTL

		Amplitude Reduction
DE Bits	%	dB
0000b	0	0
0001b	4.76	–0.42
0010b	9.52	–0.87
0011b	14.28	–1.34
0100b	19.04	–1.83
0101b	23.8	–2.36
0110b	28.56	–2.92
0111b	33.32	–3.52
1000b	38.08	–4.16
1001b	42.85	–4.86
1010b	47.61	–5.61
1011b	52.38	–6.44
1100b	57.14	–7.35
1101b	61.9	–8.38
1110b	66.66	–9.54
1111b	71.42	–10.87

34 Serial RapidIO (SRIO) SPRUE13A –September 2006

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