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SRIO Functional Description
2.3.2SERDES Macro and its Configurations
SRIO offers many benefits to customers by allowing a scalable
Additionally, there are some valuable features built into TI SERDES. System optimization can be uniquely managed to meet individual customer applications. For example, control registers within the SERDES allow you to adjust the TX differential output voltage (Vod) on a per driver basis. This allows power savings on short trace links (on the same board) by reducing the TX swing. Similarly, data edge rates can be adjusted through the control registers to help reduce any EMI affects. Unused links can be individually powered down without affecting the working links.
The SERDES macro is a
2.3.2.1Enabling the PLL
The Physical layer SERDES has a
The SERDES macro is configured with the register SERDES_CFG0_CNTL, SERDES_CFGRXn_CNTL, and SERDES_CFGTXn_CNTL, where n is the number of the macro. To enable the internal PLL, the ENPLL bit of SERDES_CFG0_CNTL (see Figure 9 and Table 5) must be set. After setting this bit, it is necessary to allow 1µs for the regulator to stabilize. Thereafter, the PLL will take no longer than 200 reference clock cycles to lock to the required frequency, provided RIOCLK and RIOCLK are stable.
Registers SERDES_CFG1_CNTL, SERDES_CFG2_CNTL, and SERDES_CFG3_CNTL are not used.
Figure 9. SERDES Macro Configuration Register 0 (SERDES_CFG0_CNTL)
31 |
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| 16 |
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| Reserved |
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15 | 10 | 9 | 8 | 7 | 6 | 5 | 1 | 0 |
Reserved |
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| Reserved |
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| MPY | ENPLL |
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LEGEND: R/W = Read/Write; R = Read only;
28 | Serial RapidIO (SRIO) | SPRUE13A |
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