Texas Instruments TMS320TCI648x manual Reset and Power Down State

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SRIO Functional Description

A transaction timeout is used by all outgoing message and direct I/O packets. It has the same value and is analogous to the request-to-response timer discussed in the RX CPPI and LSU sections, which is defined by the 24-bit value in the port response time-out CSR (See Section 2.3.3.3 ). The RapidIO Interconnect Specification states that the maximum time interval (all 1s) is between 3 and 6 seconds. A logical layer timeout occurs if the response packet is not received before a countdown timer (initialized to this CSR value) reaches zero. Since transaction responses can be acknowledged out-of-order, a timer is needed for each supported outstanding packet in the TX queue. Each outstanding packet response timer requires a

4-bit register. The register is loaded with the current timecode when the transaction is sent. Each time the timecode changes, a 4-bit compare is done to the 16 outstanding packet registers. If the register becomes equal to the timecode again, without a response being seen, then the transaction has timed out and the buffer descriptor is written.

Essentially, instead of the 24-bit value representing the period of the response timer, the period is now defined as P = (224 x 16)/F. This means the countdown timer frequency needs to be 44.7–89.5 MHz for a 6–3 second response timeout. Since the needed timer frequency is derived from the DMA bus clock (which is device dependent), the hardware supports a programmable configuration register field to properly scale the clock frequency. This configuration register field is described in the Peripheral Setting Control register (Address offset 0020h).

The CPU initiates a TX queue teardown by writing to the TX Queue Teardown command register. Teardown of a TX queue will cause the following actions:

∙No new messages will be sent.

∙All messages (single and multi-segment) already started will be completed.

–Failing to complete the message TX would leave an active receiver blocked waiting for the final segments until the transaction eventually times-out.

–Note that normal TX State Machine operation is to not send any more segments once an error response has been received on any segment. So if the receiver has also been torn-down (and is receiving error responses) multi-segment transmit will complete as soon as all in-transit segments have been responded to.

∙When all in-transit messages/segments have been responded to, teardown will be completed as follows:

–If the queue is active, the teardown bit will be set in the next buffer descriptor in the queue. The peripheral completes the teardown procedure by clearing the HDP register, setting the CP register to FFFFFFFCh, and issuing an interrupt for the given queue. The teardown command register bit is automatically cleared by the peripheral.

–If the queue is in-active (no additional buffer descriptors available), or becomes inactive after a message in transmission is completed, no buffer descriptor fields are written. The HDP register and the CP register remain unchanged. An interrupt is not issued. The teardown command register bit is automatically cleared by the peripheral.

–Because of topology differences between flow'sresponse, packets may arrive in a different order to the order of requests.

After the teardown process is complete and the interrupt is serviced by the CPU, software must re-initialize the TX queue to restart normal operation.

2.3.4.3Reset and Power Down State

Upon reset, the CPPI module must be configured by the CPU. The CPU sets up the receive and transmit queues in memory. Then the CPU updates the CPPI module with the appropriate RX/TX DMA state head descriptor pointer, so the peripheral knows with which buffer descriptor address to start. Additionally, the CPU must provide the CPPI module with initial buffer descriptor values for each data buffer.

The CPPI module can be powered down if the message passing protocol is not being supported in the application. For example, if the direct I/O protocol is being used for data transfers, powering down the CPPI module will save power. In this situation, the buffer descriptor queue SRAMs and mailbox mapper logic should be powered down. Clocks should be gated to these blocks while in the power down state. Section 2.3.10 describes this in detail.

SPRUE13A –September 2006 Serial RapidIO (SRIO) 59

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