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SRIO Registers
5.25Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR)
Each bit in this register is used to clear the corresponding status bit in ERR_RST_EVNT_ICSR. The field of ERR_RST_EVNT_ICCR are shown in Figure 86 and described in Table 76. For additional programming information, see Section 4.3.4.
Figure 86. Error, Reset, and Special Event Interrupt Condition Clear Register
(ERR_RST_EVNT_ICCR) - Address Offset 0278h
31 |
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| 17 | 16 |
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| Reserved |
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| ICC16 |
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15 | 12 | 11 | 10 | 9 | 8 | 7 | 3 | 2 | 1 | 0 |
Reserved |
| ICC11 | ICC10 | ICC9 | ICC8 |
| Reserved | ICC2 | ICC1 | ICC0 |
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LEGEND: R = Read only; W = Write only; |
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| Table 76. Error, Reset, and Special Event Interrupt Condition Clear Register | ||
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| (ERR_RST_EVNT_ICCR) Field Descriptions | |
Bit | Field | Value | Description |
Reserved | 0 | These | |
16 | ICC16 | 0 | No effect |
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| 1 | Clear bit 16 of ERR_RST_EVNT_ICSR. |
Reserved | 0 | These | |
ICCx | 0 | No effect | |
| (x = 11 to 8) | 1 | Clear bit x of ERR_RST_EVNT_ICSR. |
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Reserved | 0 | These | |
ICCy | 0 | No effect | |
| (y = 2 to 0) | 1 | Clear bit y of ERR_RST_EVNT_ICSR. |
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SPRUE13A | Serial RapidIO (SRIO) | 143 |