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SRIO Registers
Table 73. LSU Interrupt Condition Status Register (LSU_ICSR) Field Descriptions (continued)
Bit | Field | Value | Description |
1 | ICS1 | 0 | LSU1 interrupt condition not detected. |
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| 1 | LSU1 interrupt condition detected. |
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| response payload. |
0 | ICS0 | 0 | LSU1 interrupt condition not detected. |
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| 1 | LSU1 interrupt condition detected. Transaction complete, No errors |
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| this interrupt is ultimately controlled by the Interrupt Req bit of LSU1_REG4. This allows |
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| enabling/disabling on a per request basis. For optimum LSU performance, interrupt pacing should |
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| not be used on the LSU interrupts. |
140 | Serial RapidIO (SRIO) | SPRUE13A |