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Texas Instruments TMS320TCI648x manual Xoff Xon

Models: TMS320TCI648x

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SRIO Registers

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SPRUE13A –September 2006

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Texas Instruments TMS320TCI648x manual Xoff Xon

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticsr Port Link Maintenance Request CSR n SP n Lmreq List of Figures INTDSTnRATECNTL Interrupt Rate Control Register Transmit Cppi Supported Flow Mask Registers Port-Write-In Capture CSRs List of Tables PF16BCNTL Registers LSUnREG6 Registers and the Associated LSUs SP n Errdet Registers and the Associated Ports Read This First Trademarks RapidIO Architectural Hierarchy General RapidIO SystemOverview RapidIO Interconnect Architecture Physical Layer 1x/4x LP-Serial SpecificationFeatures Supported in Srio Peripheral RapidIO Feature Support in SrioTI Devices Supported By This Document Features Not SupportedStandards External Devices Requirements TI Devices Supported By This DocumentRegisters Checked For Multicast DeviceID OverviewPeripheral Data Flow Registers Checked for Multicast DeviceIDOperation Sequence Srio PacketsExample Packet Streaming Write Operation Sequence4x RapidIO Packet Data Stream Streaming-Write Class Control SymbolsFtype Ttype Packet Type Srio PinsSrio Packet Type Packet TypesComponent Block Diagram Functional OperationPin Description Srio Component Block Diagram Serdes Macro and its Configurations Enabling the PLLMPY Enpll MPY Bit Field Value DescriptionEnabling the Receiver Line Rate versus PLL Output Clock FrequencyEffect of the Rate Bits Frequency Range versus MPY ValueCDR LOS Align Term Invpair Rate Buswidth EnrxBit Field LOS EQ Bits Enabling the TransmitterCFGRX22-19 DE Bits DE Bits of SERDESCFGTXnCNTLSwing Amplitude ReductionSwing Bits Serdes Configuration ExampleSwing Bits of SERDESCFGTXnCNTL Direct I/O OperationLSU Register Field RapidIO Packet Header Field LSU Control/Command Register FieldsLSU Status Register Fields LSU Register Field FunctionBSY LSU Registers Timing Detailed Data Path Description Example Burst NwriterWrite Transactions Direct I/O TX OperationRead Transactions Direct I/O RX Operation SegmentationMessage Passing Reset and Power Down StateCppi RX Scheme for RapidIO RX OperationMessage Request Packet Bit Name Description RX DMA State Completion Pointer CP Address Offset 680h-6BChMailbox to Queue Mapping Register L n Rxumapl n Mailbox to Queue Mapping Register H n Rxumaph nField Description RX Buffer Descriptor Field DescriptionsDSP core uses this bit to reclaim buffers RX Cppi Mode Explanation Srio Functional Description TX Operation Cppi Boundary DiagramTX Buffer Descriptor Field Definitions TX DMA State Completion Pointer CP Address Offset 58h-5BChField Description TX Buffer Descriptor Field DefinitionsSsize Srio Functional Description TXQUEUECNTL3 Address Offset 7ECh TXQUEUECNTL0 Address Offset 7E0hTXQUEUECNTL1 Address Offset 7E4h TXQUEUECNTL2 Address Offset 7E8hTXQUEUECNTL23-0 TXQUEUECNTL13-0TXQUEUECNTL17-4 TXQUEUECNTL111-8TXQUEUECNTL33-0 TXQUEUECNTL37-4TXQUEUECNTL311-8 Reset and Power Down State Message Passing Software Requirements RX OperationTX Operation Initialization Example Queue MappingRX Buffer Descriptor TX Buffer Descriptor RX Buffer DescriptorsMaintenance Start Message PassingDoorbell Operation Bit LSUnREG5 Examples of Doorbellinfo Designations See FigureInfo Field Segments Reg #Congestion Control Atomic OperationsDetailed Description FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0 FlowcntlidFL9 EndiannessEndian Conversion TMS320TCI6482 Translation for MMR spaceLogical Block Reset and Power DownReset Hierarchy BusEnable and Enable Status Registers Reset and Power Down SummaryGlobal Enable and Global Enable Status Field Descriptions Valu Description e Block Enable and Block Enable Status Field DescriptionsEnstat RegisterBit FieldPeren Soft Free Software Shutdown DetailsEmulation Peripheral Control Register PCR Field DescriptionsPeripheral Control Register PCR Field Descriptions TX Buffers, Credit, and Packet ReorderingMultiple Ports With 1x Operation Unavailable Outbound Credit Single Port With 1x or 4x OperationPort Mode Register Settings Enabling the Srio Peripheral13.2 PLL, Ports, Device ID and Data Rate Initializations Set Device ID Registers Peripheral InitializationsRead register to check portx1-4 OK bit Assert the Peren bit to enable logical layer data flowBootload Capability Configuration and OperationBootload Data Movement Device WakeupRX Multicast Support 16BITDEVIDUPBOUND 16BITDEVIDLOWBOUND Multicast DeviceID OperationDaisy Chain Operation and Packet Forwarding Enabling Multicast and Packet Forwarding8BITDEVIDLOWBOUND OutboundPort 8BITDEVIDUPBOUNDFor the MAU or the RXU For an LSU or the TXUUnsolicitedrspns MsgreqtimeoutPktrspnstimeout RxiodmaaccessGeneral Description CPU InterruptsInterrupt Condition Status and Clear Registers Doorbell Interrupt Condition Status and Clear Registers Interrupt Condition Status and Clear BitsCppi Interrupt Condition Status and Clear Registers Doorbell 2 Interrupt Condition Status and Clear RegistersLSU Interrupt Condition Status and Clear Registers RX Cppi Interrupt Condition Status and Clear RegistersLSU2 Bit Associated LSU Interrupt ConditionLSU4 LSU3ICC2 ICC1 ICC0 ICS11 ICS10 ICS9 ICS8ICS2 ICS1 ICS0 ICC11 ICC10 ICC9 ICC8Interrupt Clearing Sequence for Special Event Interrupts Interrupt Function1st Step Nd Step 3rd Step Interrupt Function St Step Nd Step Rd Step Interrupt Condition Routing RegistersInterrupt Condition Routing Options Doorbell Interrupt Condition Routing RegistersICR15 ICR14 ICR13 ICR12 Cppi Interrupt Condition Routing RegistersICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0LSU Interrupt Condition Routing Registers TX Cppi Interrupt Condition Routing RegistersICR27 ICR26 ICR25 ICR24 ICR23 ICR22 ICR21 ICR20ICR19 ICR18 ICR17 ICR16 ICR31 ICR30 ICR29 ICR28ICR2 ICR1 ICR0 Interrupt Status Decode RegistersInterrupt Status Decode Register INTDSTnDECODE Interrupt Pacing Interrupt GenerationINTDSTnRATECNTL Interrupt Rate Control Register Interrupt Handling101 Introduction Serial RapidIO Srio RegistersOffset Acronym Register Description Offset Acronym Register Description Serial RapidIO Srio RegistersINTDST6DECODE INTDST3DECODEINTDST4DECODE INTDST5DECODEQUEUE1TXDMAHDP QUEUE2RXDMACP QUEUE15RXDMAHDPQUEUE0RXDMACP QUEUE1RXDMACPRXUMAPH8 RXUMAPL7RXUMAPH7 RXUMAPL8RXUMAPH31 RXUMAPL30RXUMAPH30 RXUMAPL31SP1CTL SP2SILENCETIMER SpipdiscoverytimerSP0SILENCETIMER SP1SILENCETIMERClass REV Peripheral Identification Register PIDPeripheral ID Register PID Field Descriptions TypeHalts Peripheral Control Register PCRPeripheral Settings Control Register Persetcntl Prescalerselect Enable Serdes PLL Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Register GblenPeripheral Global Enable Status Register Gblenstat MMRs for the Srio peripheral Register Address Offset Associated Block Block n Enable Register BLKnENBlock n Enable Registers and the Associated Blocks Block n Enable Register BLKnEN Field DescriptionsBlock n Enable Status Registers and the Associated Blocks Block n Enable Status Register BLKnENSTAT16BNODEID RapidIO DEVICEID1 Register DEVICEIDREG1RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions 8BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions RapidIO DEVICEID2 Register DEVICEIDREG2Register Address Offset PF16BCNTL RegistersPF8BCNTL Registers Packet Forwarding Register n for 8-Bit Device IDs PF8BCNTLnRegister Address Offset Associated Port SERDESCFGRXnCNTL Registers and the Associated PortsVia a 50 pF capacitor to Vssa 127 SERDESCFGTXnCNTL Registers and the Associated Ports SERDESCFGTX3CNTLSwing Invpair Rate Buswidth Entx 129 SERDESCFGnCNTL Registers and the Associated Ports Serdes Macro Configuration Register n SERDESCFGnCNTL131 Doorbell nICSR Registers DOORBELLn Interrupt Condition Status Register DOORBELLnICSRDoorbell nICCR Registers DOORBELLn Interrupt Condition Clear Register DOORBELLnICCRRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr ICS31 LSU Interrupt Condition Status Register Lsuicsr139 140 LSU Interrupt Condition Clear Register Lsuiccr 31-17 Reserved These reserved bits return 0s when read Errrstevnticcr Field Descriptions Field Value Description Doorbell nICRR Registers= 0 to Eight interrupt destinations INTDST0-INTDST7 146 LSU Interrupt Condition Routing Registers LSUICRR0-LSUICRR3 LSU Interrupt Condition Routing Register Field Descriptions = 0 to 2, 8 to 11, Interrupt destinations INTDST0-INTDST7 Destination Interrupt Status Decode Register INTDSTnDECODETX buffer descriptor queue 4 bit 4 of Txcppiicsr ∙ Doorbell 0, bit 15 bit 15 of DOORBELL0ICSR ISD3 ISD2ISD1 Countdownvalue INTDSTn Interrupt Rate Control Register INTDSTnRATECNTLAddressmsb LSUn Control Register 0 LSUnREG0LSUnREG0 Registers and the Associated LSUs LSUn Control Register 0 LSUnREG0 Field DescriptionsLSUn Control Register 1 LSUnREG1 Field Descriptions For packet type 8 maintenance packetLSUn Control Register 1 LSUnREG1 LSUnREG1 Registers and the Associated LSUsDspaddress LSUn Control Register 2 LSUnREG2LSUnREG2 Registers and the Associated LSUs LSUn Control Register 2 LSUnREG2 Field DescriptionsBytecount LSUn Control Register 3 LSUnREG3LSUnREG3 Registers and the Associated LSUs LSUn Control Register 3 LSUnREG3 Field DescriptionsLSUn Control Register 4 LSUnREG4 LSUnREG4 Registers and the Associated LSUsLSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 5 LSUnREG5 LSUnREG5 Registers and the Associated LSUsLSUn Control Register 5 LSUnREG5 Field Descriptions Completioncode BSY LSUn Control Register 6 LSUnREG6LSUnREG6 Registers and the Associated LSUs LSUn Control Register 6 LSUnREG6 Field DescriptionsLSUnFLOWMASKS Registers and the Associated LSUs LSUn Congestion Control Flow Mask Register LSUnFLOWMASKSLSU n supports Flow 8 from table entry Register QUEUEnTXDMAHDP RegistersQUEUEnTXDMACP Registers QUEUEnRXDMAHDP Registers Rxcp QUEUEnRXDMACP RegistersTransmit Queue Teardown Register Txqueueteardown Txcppiflowmasks Registers and the Associated TX Queues TX Queue n Flowmask Field Descriptions Queue n supports Flow 12 from table entry Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Field Descriptions Receive Cppi Control Register RxcppicntlTXQUEUECNTL3 Address Offset 07ECh TXQUEUECNTL0 Address Offset 07E0hTXQUEUECNTL1 Address Offset 07E4h TXQUEUECNTL2 Address Offset 07E8hField Pair TXQUEUECNTL211-8 Mailbox to Queue Mapping Registers RXUMAPLn and RXUMAPHn 0890h Mapper Letter LettermaskFor a single-segment message For a multi-segment messageSegmentmapping QueueidFlowcntl n Registers Flow Control Table Entry Register n FLOWCNTLnDeviceidentity Device Identity CAR DevidDevice Identity CAR Devid Field Descriptions Deviceidentity Devicevendoridentity31-0 Device Information CAR DevinfoDevice Information CAR Devinfo Field Descriptions DevicerevAssyidentity Assembly Identity CAR AsblyidAssembly Identity CAR Asblyid Field Descriptions Assyidentity AssyvendoridentityAssyrev Assembly Information CAR AsblyinfoAssembly Information CAR Asblyinfo Field Descriptions ExtendedfeaturesptrProcessing Element Features CAR Pefeat Field Descriptions Processing Element Features CAR PefeatSource and target of an operation. All PEs shall at minimum Source Operations CAR Srcop Field Descriptions Source Operations CAR SrcopResp Andswap Atomic Destination Operations CAR DestopDestination Operations CAR Destop Field Descriptions Read Write Streamwrite Writewith Datamess DoorbellProcessing Element Logical Layer Control CSR Pellctl AddressingExtendedaddressingcontrol Local Configuration Space Base Address 0 CSR Lclcfghbar LcsbaBit Field Value Local Configuration Space Base Address 1 CSR Lclcfgbar Largebasedeviceid Base Device ID CSR BaseidBase Device ID CSR Baseid Field Descriptions BasedeviceidHostbasedeviceid Host Base Device ID Lock CSR HostbaseidlockComponent Tag CSR Comptag Component Tag CSR Comptag Field DescriptionsComponenttag Efptr Efptr EfidPort Link Timeout Control CSR Spltctl Field Descriptions TimeoutvaluePort Link Time-Out Control CSR Spltctl Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Field Descriptions Port General Control CSR SpgenctlSP2LMREQ Port Link Maintenance Request CSR n SPnLMREQCommand SPnLMREQ Registers and the Associated PortsSPnLMRESP Registers and the Associated Ports Port Link Maintenance Response CSR n SPnLMRESPSPnACKIDSTAT Registers and the Associated Ports Port Local AckID Status CSR n SPnACKIDSTATPort Error and Status CSR n SPnERRSTAT Port Error and Status CSR n SPnERRSTAT Field DescriptionsSPnERRSTAT Registers and the Associated Ports Inputerrorstp OutputerrorencOutputerrorstp InputerrorencPortuninitialized PortokPort Control CSR n SPnCTL SPnCTL Registers and the Associated PortsPort Control CSR n SPnCTL Field Descriptions Errorcheckdisable PortdisableOutputportenable InputportenableRather than a parallel port Error Reporting Block Header Register Errrptbh Logical/Transport Layer Error Detect CSR Errdet RX I/O DMA access error Logical/Transport Layer Error Enable CSR Erren Rxcppisecurityenable PktresptimeoutenableUnsolicitedrespenable UnsupportedtransenableADDRESS6332 Logical/Transport Layer High Address Capture CSR HaddrcaptLogical/Transport Layer Address Capture CSR Addrcapt ADDRESS313Xamsbs Msbdestid Logical/Transport Layer Device ID Capture CSR IdcaptMsbdestid Destid Msbsourceid SourceidFtype Logical/Transport Layer Control Capture CSR CtrlcaptFtype Ttype Msginfo ImpspecificDeviceid Port-Write Target Device ID CSR PwtgtidPort-Write Target Device ID CSR Pwtgtid Field Descriptions DeviceidmsbPort Error Detect CSR n SPnERRDET Port Error Detect CSR n SPnERRDET Field DescriptionsSPnERRDET Registers and the Associated Ports Rcvdpktnotaccpt ProtocolerrorDelineationerror LinktimeoutPort Error Rate Enable CSR n SPnRATEEN Port Error Rate Enable CSR n SPnRATEEN Field DescriptionsSPnRATEEN Registers and the Associated Ports Pktunexpectedackiden ProtocolerrorenDelineationerroren LinktimeoutenSPnERRATTRCAPTDBG0 Registers and the Associated Ports Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0SPnERRCAPTDBG1 Registers and the Associated Ports Port n Error Capture CSR 1 SPnERRCAPTDBG1Description Case of a control-symbol error Case of a packet errorSPnERRCAPTDBG2 Registers and the Associated Ports Port n Error Capture CSR 2 SPnERRCAPTDBG2SPnERRCAPTDBG3 Registers and the Associated Ports Port n Error Capture CSR 3 SPnERRCAPTDBG3SPnERRCAPTDBG4 Registers and the Associated Ports Port n Error Capture CSR 4 SPnERRCAPTDBG4Port Error Rate CSR n SPnERRRATE Port Error Rate CSR n SPnERRRATE Field DescriptionsSPnERRRATE Registers and the Associated Ports SPnERRTHRESH Registers and the Associated Ports Port Error Rate Threshold CSR n SPnERRTHRESHPwtimer DiscoverytimerPort IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR SpipmodePwirq RstenRstcs PwenPort IP Prescaler Register Ipprescal Port IP Prescaler Register Ipprescal Field DescriptionsPrescale Port-Write-In Capture CSR Field Descriptions Port-Write-In Capture CSRs SPIPPWINCAPT0-3Portid Port Reset Option CSR n SPnRSTOPTPort Reset Option CSR n SPnRSTOPT Field Descriptions SPnRSTOPT Registers and the Associated PortsSPnCTLINDEP Registers and the Associated Ports Port Control Independent Register n SPnCTLINDEPMaxretryen SenddbgpktIlltransen IlltranserrPort Silence Timer n Register SPnSILENCETIMER SPnSILENCETIMER Registers and the Associated PortsSilencetimer SPnMULTEVNTCS Registers and the Associated Ports MultevntcsBit Field Value Description 31-0 STYPE0 Port Control Symbol Transmit n Register SPnCSTXSPnCSTX Registers and the Associated Ports STYPE0 PAR0 PAR1 STYPE1 CMD CsembIndex Comptag Ctrlcapt Devinfo Pellctl Haddrcapt Lsuicsr 237 Pefeat 232 Srio Registers Rxcppicntl Rxcppiiccr Rxcppiicrr RXCPPIICRR2 Rxcppiicsr Broken link Degraded link Maximum retry error at port n Txqueueteardown Xoff Xon Important Notice