Texas Instruments TMS320TCI648x manual LSUn Congestion Control Flow Mask Register LSUnFLOWMASKS

Models: TMS320TCI648x

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SRIO Registers

5.40 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS)

There are four of these registers, one for each LSU (see Table 101). The fields of an

LSUn_FLOW_MASKS register are summarized by Figure 101 and described in Table 102. The 16 bits within each FLOW_MASK field are summarized by Figure 102 and Table 103. For additional programming see Section 2.3.8.

Table 101. LSUn_FLOW_MASKS Registers and the Associated LSUs

Register

Address Offset

LSU

LSU1_FLOW_MASKS

041Ch

LSU1

LSU2_FLOW_MASKS

043Ch

LSU2

LSU3_FLOW_MASKS

045Ch

LSU3

LSU4_FLOW_MASKS

047Ch

LSU4

Figure 101. LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS)

31

16

15

0

 

Reserved

 

FLOW_MASK

 

R-00h

 

R/W-FFh

LEGEND: R/W = Read/Write; R = Read only; -n= Value after reset

Table 102. LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS) Field Descriptions

Bit

Field

Value

Description

31–16

Reserved

00h

These read-only bits return 0s when read.

15–0

FLOW_MASK

00h-FFh

Flow mask for LSUn

Figure 102. LSUn FLOW_MASK Fields

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FL15

FL14

FL13

FL12

FL11

FL10

FL9

FL8

FL7

FL6

FL5

FL4

FL3

FL2

FL1

FL0

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

LEGEND: R = Read; W = Write; -n= Value after reset

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 103. LSUn FLOW_MASK Fields

Bit

Field

Value

Description

15

FL15

0

LSUn does not support Flow 15 from table entry

 

 

1

LSUn supports Flow 15 from table entry

14

FL14

0

LSUn does not support Flow 14 from table entry

 

 

1

LSUn supports Flow 14 from table entry

13

FL13

0

LSUn does not support Flow 13 from table entry

 

 

1

LSUn supports Flow 13 from table entry

12

FL12

0

LSUn does not support Flow 12 from table entry

 

 

1

LSUn supports Flow 12 from table entry

11

FL11

0

LSUn does not support Flow 11 from table entry

 

 

1

LSUn supports Flow 11 from table entry

10

FL10

0

LSUn does not support Flow 10 from table entry

 

 

1

LSUn supports Flow 10 from table entry

9

FL9

0

LSUn does not support Flow 9 from table entry

 

 

1

LSUn supports Flow 9 from table entry

162

Serial RapidIO (SRIO)

 

SPRUE13A –September 2006

 

 

 

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Texas Instruments TMS320TCI648x manual LSUn Congestion Control Flow Mask Register LSUnFLOWMASKS