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SRIO Registers
in SRIO component block diagram 26 PID register 111
pins/differential signals 25
PKT_RESP_TIMEOUT_ENABLE field of ERR_EN 212 PKT_RSPNS_TIMEOUT field of ERR_DET 210
PKT_UNEXPECTED_ACKID_EN field of SPn_RATE_EN 221
PKT_UNEXPECTED_ACKID field of SPn_ERR_DET
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PLL block for SERDES | 21, 28 |
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PLL enable bit 131 |
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PLL multiply field for SERDES macro | 131 |
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PLL output clock frequency versus line rate | 29 | ||
pointer to the next block in the data structure | 196 | ||
polarity inversion bit |
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for RIORX and RIORX (reception) | 126 |
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for RIOTX and RIOTX (transmission) 128 |
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port 0 enable status bit | 117 |
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port 1 enable status bits | 117 |
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port 2 enable status bits | 117 |
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port 3 enable status bits | 117 |
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PORT_DISABLE field of SPn_CTL 206 PORT_ERROR field of SPn_ERR_STAT 203 PORT_ID field of SPn_RST_OPT 235
port_id field of TX buffer descriptor | 52 |
PORT_LOCKOUT field of SPn_CTL | 206 |
PORT_OK field of SPn_ERR_STAT | 203 |
PORT_TYPE field of SPn_CTL 206
PORT_UNINITIALIZED field of SPn_ERR_STAT 203
PORT_WIDTH_OVERRIDE field of SPn_CTL | 206 | |||||
PORT_WIDTH field of SPn_CTL | 206 |
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PORT_WRITE_PND field of SPn_ERR_STAT | 203 | |||||
PORT_WRITE field of DEST_OP | 189 |
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PORT_WRITE field of SRC_OP | 188 |
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port attributes error capture CSR 0 223 |
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port control CSR 206 |
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port control independent register | 236 |
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port control symbol transmit registers | 240 |
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port error and status CSR | 203 |
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port error capture CSR 1 | 224 |
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port error capture CSR 2 | 225 |
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port error capture CSR 3 | 226 |
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port error capture CSR 4 | 227 |
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port error detect CSR 219 |
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port error rate CSR 228 |
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port error rate enable CSR | 221 |
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port error rate threshold CSR | 229 |
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port general control CSR | 199 |
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port ID field for | 235 | |||||
port IP discovery timer for 4x mode register | 230 | |||||
port IP mode CSR 231 |
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port IP prescaler register | 233 |
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port link maintenance request CSR | 200 |
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port link maintenance response CSR | 201 |
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port link | 197 |
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port local ackID status CSR | 202 |
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250Index
port
239 |
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port n error capture |
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control information field | 224 |
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packet header bytes 0 to 3 field | 224 | |||||
packet header bytes 4 to 7 field | 225 | |||||
packet header bytes 8 to 11 field | 226 | |||||
packet header bytes 12 to 15 field | 227 | |||||
type of error field | 223 |
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type of information field | 223 |
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valid information field | 223 |
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port reset option CSR | 235 |
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port response | 198 | |||||
ports |
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enable bits 119 |
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enable status bits | 120 |
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in SRIO component block diagram | 26 | |||||
port silence timer registers | 238 |
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231 | ||||||
234 |
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234 |
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232 | ||||||
232 | ||||||
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204 |
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230 |
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235 |
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posted WRITE operations during direct I/O transmission
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power down state |
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CPPI module 59 |
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Load/Store module 43 |
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PRESCALE field of IP_PRESCAL | 233 |
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PRESCALER_SELECT field of PER_SET_CNTL | 113 | ||||
pri field of RX buffer descriptor | 47 |
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pri field of TX buffer descriptor | 52 |
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priority arbiter for |
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PRIORITY field of LSUn_REG4 | 159 |
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priority of doorbell packets 64 |
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priority transmit credit thresholds | 113 |
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processing element features CAR | 186 |
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processing element logical layer control CSR | 190 |
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PROCESSOR field of PE_FEAT |
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processor present field 186 |
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PROMISCUOUS field of RXU_MAP_Hn |
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description | 178 |
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introduction | 45 |
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PROTOCOL_ERROR_EN field of SPn_RATE_EN | 221 | ||||
PROTOCOL_ERROR field of SPn_ERR_DET 219 | |||||
PW_CAPT0 field of SP_IP_PW_IN_CAPT0 | 234 |
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PW_CAPT1 field of SP_IP_PW_IN_CAPT1 | 234 |
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PW_CAPT2 field of SP_IP_PW_IN_CAPT2 | 234 |
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PW_CAPT3 field of SP_IP_PW_IN_CAPT3 | 234 |
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SPRUE13A