Texas Instruments TMS320TCI648x manual 232

SRIO Registers

in SRIO component block diagram 26 PID register 111

pins/differential signals 25

PKT_RESP_TIMEOUT_ENABLE field of ERR_EN 212 PKT_RSPNS_TIMEOUT field of ERR_DET 210

PKT_UNEXPECTED_ACKID_EN field of SPn_RATE_EN 221

PKT_UNEXPECTED_ACKID field of SPn_ERR_DET

219
PLL block for SERDES	21, 28
PLL enable bit 131
PLL multiply field for SERDES macro		131
PLL output clock frequency versus line rate			29
pointer to the next block in the data structure			196
polarity inversion bit
for RIORX and RIORX (reception)		126
for RIOTX and RIOTX (transmission) 128
port 0 enable status bit	117
port 1 enable status bits	117
port 2 enable status bits	117
port 3 enable status bits	117

PORT_DISABLE field of SPn_CTL 206 PORT_ERROR field of SPn_ERR_STAT 203 PORT_ID field of SPn_RST_OPT 235

port_id field of TX buffer descriptor	52
PORT_LOCKOUT field of SPn_CTL	206
PORT_OK field of SPn_ERR_STAT	203

PORT_TYPE field of SPn_CTL 206

PORT_UNINITIALIZED field of SPn_ERR_STAT 203

PORT_WIDTH_OVERRIDE field of SPn_CTL						206
PORT_WIDTH field of SPn_CTL			206
PORT_WRITE_PND field of SPn_ERR_STAT						203
PORT_WRITE field of DEST_OP			189
PORT_WRITE field of SRC_OP			188
port attributes error capture CSR 0 223
port control CSR 206
port control independent register			236
port control symbol transmit registers				240
port error and status CSR	203
port error capture CSR 1	224
port error capture CSR 2	225
port error capture CSR 3	226
port error capture CSR 4	227
port error detect CSR 219
port error rate CSR 228
port error rate enable CSR	221
port error rate threshold CSR		229
port general control CSR	199
port ID field for port-write request at port n					235
port IP discovery timer for 4x mode register					230
port IP mode CSR 231
port IP prescaler register	233
port link maintenance request CSR				200
port link maintenance response CSR				201
port link time-out control CSR		197
port local ackID status CSR		202

250Index

port multicast-event control symbol request registers

239
port n error capture
control information field			224
packet header bytes 0 to 3 field					224
packet header bytes 4 to 7 field					225
packet header bytes 8 to 11 field						226
packet header bytes 12 to 15 field						227
type of error field	223
type of information field			223
valid information field		223
port reset option CSR		235
port response time-out control CSR						198
ports
enable bits 119
enable status bits	120
in SRIO component block diagram						26
port silence timer registers			238
port-write error reporting disable field						231
port-write generation support for destination device 189
port-write generation support for source device 188
port-write-in capture CSR			234
port-write-in capture payload				234
port-write-in interrupt enable field					232
port-write-in interrupt status field					232
port-write maintenance operation					63
port-write pending status field				204
port-write repeat period field				230
port-write request port ID			235
port-write target device ID CSR 218

posted WRITE operations during direct I/O transmission

41
power down state
CPPI module 59
Load/Store module 43
PRESCALE field of IP_PRESCAL			233
PRESCALER_SELECT field of PER_SET_CNTL					113
pri field of RX buffer descriptor		47
pri field of TX buffer descriptor		52
priority arbiter for single-port transmission 76
PRIORITY field of LSUn_REG4		159
priority of doorbell packets 64
priority transmit credit thresholds			113
processing element features CAR			186
processing element logical layer control CSR				190
PROCESSOR field of PE_FEAT			186
processor present field 186
PROMISCUOUS field of RXU_MAP_Hn
description	178
introduction	45
PROTOCOL_ERROR_EN field of SPn_RATE_EN					221
PROTOCOL_ERROR field of SPn_ERR_DET 219
PW_CAPT0 field of SP_IP_PW_IN_CAPT0				234
PW_CAPT1 field of SP_IP_PW_IN_CAPT1				234
PW_CAPT2 field of SP_IP_PW_IN_CAPT2				234
PW_CAPT3 field of SP_IP_PW_IN_CAPT3				234

SPRUE13A –September 2006

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