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SRIO Registers
5.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)
There are four of these registers, to support four ports (see ). The general form for a SERDES receive channel configuration register is summarized by Figure 74 and Table 57. See Section 2.3.2.2 for a complete explanation of the programming of these registers.
Table 56. SERDES_CFGRXn_CNTL Registers and the Associated Ports
Register | Address Offset | Associated Port |
SERDES_CFGRX0_CNTL | 0100h | Port 0 |
SERDES_CFGRX1_CNTL | 0104h | Port 1 |
SERDES_CFGRX2_CNTL | 0108h | Port 2 (TMS320TCI6482 Only) |
SERDES_CFGRX3_CNTL | 010Ch | Port 3 (TMS320TCI6482 Only) |
Figure 74. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)
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| 26 | 25 | 24 | 23 | 22 |
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| 19 | 18 |
| 16 |
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| Reserved |
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| Reserved |
| — |
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| EQ |
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| CDR |
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| (write 0s) |
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15 | 14 | 13 | 12 | 11 | 10 |
| 8 |
| 7 | 6 | 5 | 4 |
| 2 | 1 | 0 |
LOS |
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| ALIGN | — |
| TERM | INVPAIR |
| RATE |
| BUSWIDTH |
| — | ENRX | ||
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| (write 001b) |
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LEGEND: R/W = Read/Write; R = Read only; |
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Table 57. SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL) Field
Descriptions
Bit | Field | Value | Description |
Reserved | 000000b | These | |
Reserved | 00b | Always write 0s to these reserved bits. | |
23 | Reserved | 0 | This |
EQ | Equalizer. Enables and configures the adaptive equalizer to compensate for loss | ||
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| in the transmission media. For the selectable values, see Table 58. |
CDR |
| Clock/data recovery. Configures the clock/data recovery algorithm. | |
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| 000b | First order. Phase offset tracking up to ±488 ppm. |
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| 001b | Second order. Highest precision frequency offset matching but poorest response |
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| to changes in frequency offset, and longest lock time. Suitable for use in systems |
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| with fixed frequency offset. |
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| 010b | Second order. Medium precision frequency offset matching, frequency offset |
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| change response, and lock time. |
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| 011b | Second order. Best response to changes in frequency offset and fastest lock time, |
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| but lowest precision frequency offset matching. Suitable for use in systems with |
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| spread spectrum clocking. |
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| 100b | First order with fast lock. Phase offset tracking up to ±1953 ppm in the presence of |
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| ..10101010.. training pattern, and ±448 ppm otherwise. |
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| 101b | Second order with fast lock. As per setting 001, but with improved response to |
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| changes in frequency offset when not close to lock. |
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| 110b | Second order with fast lock. As per setting 010, but with improved response to |
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| changes in frequency offset when not close to lock. |
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| 111b | Second order with fast lock. As per setting 011, but with improved response to |
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| changes in frequency offset when not close to lock. |
SPRUE13A | Serial RapidIO (SRIO) | 125 |
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