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Texas Instruments TMS320TCI648x manual Peripheral Control Register PCR, Halts

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SRIO Registers

5.3Peripheral Control Register (PCR)

The peripheral control register (PCR) contains a bit that enables or disables data flow in the logical layer of the entire peripheral. In addition, the PCR has emulation control bits that control the peripheral behavior during emulation halts. PCR is shown in Figure 64 and described in Table 42. For additional programming information, see Section 2.3.11.

Figure 64. Peripheral Control Register (PCR) - Address Offset 0004h

31				16
Reserved
R-0
15	3	2	1	0
Reserved		PEREN	SOFT	FREE
R-0		R/W-0	R/W-0	R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n= Value after reset

Table 42. Peripheral Control Register (PCR) Field Descriptions

Bit	Field	Value	Description
31–3	Reserved	0	These read-only bits return 0s when read.
2	PEREN		Peripheral flow control enable. Controls the flow of data in the logical layer of the peripheral. As an
			initiator, it will prevent TX transaction generation; as a target, it will disable incoming requests. This
			should be the last enable bit to toggle when bringing the device out of reset to begin normal
			operation.
		0	Data flow control is disabled.
		1	Data flow control is enabled.
1	SOFT		Soft stop. This bit and the FREE bit determine how the SRIO peripheral behaves during emulation
			halts.
		0	Hard stop. All status registers are frozen in default state. (This mode is not supported on the SRIO
			peripheral.)
		1	Soft stop
0	FREE		Free run
		0	The SOFT bit takes effect.
		1	Free run. Peripheral ignores the emulation suspend signal and functions normally.

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Serial RapidIO (SRIO)

SPRUE13A –September 2006

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Texas Instruments TMS320TCI648x manual Peripheral Control Register PCR, Halts

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticsr Port Link Maintenance Request CSR n SP n Lmreq List of Figures INTDSTnRATECNTL Interrupt Rate Control Register Transmit Cppi Supported Flow Mask Registers Port-Write-In Capture CSRs List of Tables PF16BCNTL Registers LSUnREG6 Registers and the Associated LSUs SP n Errdet Registers and the Associated Ports Read This First Trademarks General RapidIO System RapidIO Architectural HierarchyOverview Physical Layer 1x/4x LP-Serial Specification RapidIO Interconnect ArchitectureRapidIO Feature Support in Srio Features Supported in Srio PeripheralFeatures Not Supported Standards External Devices RequirementsTI Devices Supported By This Document TI Devices Supported By This DocumentOverview Peripheral Data FlowRegisters Checked for Multicast DeviceID Registers Checked For Multicast DeviceIDSrio Packets Operation SequenceOperation Sequence Example Packet Streaming WriteControl Symbols 4x RapidIO Packet Data Stream Streaming-Write ClassSrio Pins Srio Packet TypePacket Types Ftype Ttype Packet TypeFunctional Operation Component Block DiagramPin Description Srio Component Block Diagram Enabling the PLL Serdes Macro and its ConfigurationsMPY Enpll Bit Field Value Description MPYLine Rate versus PLL Output Clock Frequency Effect of the Rate BitsFrequency Range versus MPY Value Enabling the ReceiverLOS Align Term Invpair Rate Buswidth Enrx CDRBit Field LOS Enabling the Transmitter EQ BitsCFGRX22-19 DE Bits of SERDESCFGTXnCNTL SwingAmplitude Reduction DE BitsSerdes Configuration Example Swing Bits of SERDESCFGTXnCNTLDirect I/O Operation Swing BitsLSU Control/Command Register Fields LSU Register Field RapidIO Packet Header FieldLSU Register Field Function LSU Status Register FieldsBSY LSU Registers Timing Example Burst Nwriter Detailed Data Path DescriptionDirect I/O TX Operation Write TransactionsRead Transactions Segmentation Direct I/O RX OperationReset and Power Down State Message PassingRX Operation Cppi RX Scheme for RapidIOMessage Request Packet RX DMA State Completion Pointer CP Address Offset 680h-6BCh Mailbox to Queue Mapping Register L n Rxumapl nMailbox to Queue Mapping Register H n Rxumaph n Bit Name DescriptionRX Buffer Descriptor Field Descriptions Field DescriptionDSP core uses this bit to reclaim buffers RX Cppi Mode Explanation Srio Functional Description Cppi Boundary Diagram TX OperationTX DMA State Completion Pointer CP Address Offset 58h-5BCh TX Buffer Descriptor Field DefinitionsTX Buffer Descriptor Field Definitions Field DescriptionSsize Srio Functional Description TXQUEUECNTL0 Address Offset 7E0h TXQUEUECNTL1 Address Offset 7E4hTXQUEUECNTL2 Address Offset 7E8h TXQUEUECNTL3 Address Offset 7EChTXQUEUECNTL13-0 TXQUEUECNTL17-4TXQUEUECNTL111-8 TXQUEUECNTL23-0TXQUEUECNTL37-4 TXQUEUECNTL33-0TXQUEUECNTL311-8 Reset and Power Down State RX Operation Message Passing Software RequirementsTX Operation Queue Mapping Initialization ExampleRX Buffer Descriptor RX Buffer Descriptors TX Buffer DescriptorStart Message Passing MaintenanceDoorbell Operation Examples of Doorbellinfo Designations See Figure Info Field SegmentsReg # Bit LSUnREG5Atomic Operations Congestion ControlDetailed Description Flowcntlid FL9 FL8 FL7 FL6 FL5 FL4 FL3 FL2 FL1 FL0Endianness FL9Translation for MMR space Endian Conversion TMS320TCI6482Reset and Power Down Reset HierarchyBus Logical BlockReset and Power Down Summary Enable and Enable Status RegistersGlobal Enable and Global Enable Status Field Descriptions Block Enable and Block Enable Status Field Descriptions EnstatRegisterBit Field Valu Description eSoftware Shutdown Details EmulationPeripheral Control Register PCR Field Descriptions Peren Soft FreeTX Buffers, Credit, and Packet Reordering Peripheral Control Register PCR Field DescriptionsMultiple Ports With 1x Operation Single Port With 1x or 4x Operation Unavailable Outbound CreditEnabling the Srio Peripheral Port Mode Register Settings13.2 PLL, Ports, Device ID and Data Rate Initializations Peripheral Initializations Set Device ID RegistersAssert the Peren bit to enable logical layer data flow Bootload CapabilityConfiguration and Operation Read register to check portx1-4 OK bitDevice Wakeup Bootload Data MovementRX Multicast Support Multicast DeviceID Operation Daisy Chain Operation and Packet ForwardingEnabling Multicast and Packet Forwarding 16BITDEVIDUPBOUND 16BITDEVIDLOWBOUNDOutbound Port8BITDEVIDUPBOUND 8BITDEVIDLOWBOUNDFor an LSU or the TXU For the MAU or the RXUMsgreqtimeout PktrspnstimeoutRxiodmaaccess UnsolicitedrspnsCPU Interrupts General DescriptionInterrupt Condition Status and Clear Registers Interrupt Condition Status and Clear Bits Doorbell Interrupt Condition Status and Clear RegistersDoorbell 2 Interrupt Condition Status and Clear Registers Cppi Interrupt Condition Status and Clear RegistersRX Cppi Interrupt Condition Status and Clear Registers LSU Interrupt Condition Status and Clear RegistersBit Associated LSU Interrupt Condition LSU4LSU3 LSU2ICS11 ICS10 ICS9 ICS8 ICS2 ICS1 ICS0ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0Interrupt Function Interrupt Clearing Sequence for Special Event Interrupts1st Step Nd Step 3rd Step Interrupt Condition Routing Registers Interrupt Condition Routing OptionsDoorbell Interrupt Condition Routing Registers Interrupt Function St Step Nd Step Rd StepCppi Interrupt Condition Routing Registers ICR7 ICR6 ICR5 ICR4ICR3 ICR2 ICR1 ICR0 ICR15 ICR14 ICR13 ICR12TX Cppi Interrupt Condition Routing Registers LSU Interrupt Condition Routing RegistersICR23 ICR22 ICR21 ICR20 ICR19 ICR18 ICR17 ICR16ICR31 ICR30 ICR29 ICR28 ICR27 ICR26 ICR25 ICR24Interrupt Status Decode Registers ICR2 ICR1 ICR0Interrupt Status Decode Register INTDSTnDECODE Interrupt Generation Interrupt PacingInterrupt Handling INTDSTnRATECNTL Interrupt Rate Control Register101 Serial RapidIO Srio Registers IntroductionOffset Acronym Register Description Serial RapidIO Srio Registers Offset Acronym Register DescriptionINTDST3DECODE INTDST4DECODEINTDST5DECODE INTDST6DECODEQUEUE1TXDMAHDP QUEUE15RXDMAHDP QUEUE0RXDMACPQUEUE1RXDMACP QUEUE2RXDMACPRXUMAPL7 RXUMAPH7RXUMAPL8 RXUMAPH8RXUMAPL30 RXUMAPH30RXUMAPL31 RXUMAPH31SP1CTL Spipdiscoverytimer SP0SILENCETIMERSP1SILENCETIMER SP2SILENCETIMERPeripheral Identification Register PID Peripheral ID Register PID Field DescriptionsType Class REVPeripheral Control Register PCR HaltsPeripheral Settings Control Register Persetcntl Prescalerselect Enable Serdes PLL Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field DescriptionsPeripheral Global Enable Status Register Gblenstat MMRs for the Srio peripheral Block n Enable Register BLKnEN Block n Enable Registers and the Associated BlocksBlock n Enable Register BLKnEN Field Descriptions Register Address Offset Associated BlockBlock n Enable Status Register BLKnENSTAT Block n Enable Status Registers and the Associated BlocksRapidIO DEVICEID1 Register DEVICEIDREG1 RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions8BNODEID 16BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field DescriptionsPF16BCNTL Registers Register Address OffsetPacket Forwarding Register n for 8-Bit Device IDs PF8BCNTLn PF8BCNTL RegistersSERDESCFGRXnCNTL Registers and the Associated Ports Register Address Offset Associated PortVia a 50 pF capacitor to Vssa 127 SERDESCFGTX3CNTL SERDESCFGTXnCNTL Registers and the Associated PortsSwing Invpair Rate Buswidth Entx 129 Serdes Macro Configuration Register n SERDESCFGnCNTL SERDESCFGnCNTL Registers and the Associated Ports131 DOORBELLn Interrupt Condition Status Register DOORBELLnICSR Doorbell nICSR RegistersDOORBELLn Interrupt Condition Clear Register DOORBELLnICCR Doorbell nICCR RegistersRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr LSU Interrupt Condition Status Register Lsuicsr ICS31139 140 LSU Interrupt Condition Clear Register Lsuiccr 31-17 Reserved These reserved bits return 0s when read Errrstevnticcr Field Descriptions Doorbell nICRR Registers Field Value Description= 0 to Eight interrupt destinations INTDST0-INTDST7 146 LSU Interrupt Condition Routing Registers LSUICRR0-LSUICRR3 LSU Interrupt Condition Routing Register Field Descriptions = 0 to 2, 8 to 11, Interrupt destinations INTDST0-INTDST7 Interrupt Status Decode Register INTDSTnDECODE DestinationTX buffer descriptor queue 4 bit 4 of Txcppiicsr ∙ Doorbell 0, bit 15 bit 15 of DOORBELL0ICSR ISD2 ISD3ISD1 INTDSTn Interrupt Rate Control Register INTDSTnRATECNTL CountdownvalueLSUn Control Register 0 LSUnREG0 LSUnREG0 Registers and the Associated LSUsLSUn Control Register 0 LSUnREG0 Field Descriptions AddressmsbFor packet type 8 maintenance packet LSUn Control Register 1 LSUnREG1LSUnREG1 Registers and the Associated LSUs LSUn Control Register 1 LSUnREG1 Field DescriptionsLSUn Control Register 2 LSUnREG2 LSUnREG2 Registers and the Associated LSUsLSUn Control Register 2 LSUnREG2 Field Descriptions DspaddressLSUn Control Register 3 LSUnREG3 LSUnREG3 Registers and the Associated LSUsLSUn Control Register 3 LSUnREG3 Field Descriptions BytecountLSUnREG4 Registers and the Associated LSUs LSUn Control Register 4 LSUnREG4LSUn Control Register 4 LSUnREG4 Field Descriptions LSUnREG5 Registers and the Associated LSUs LSUn Control Register 5 LSUnREG5LSUn Control Register 5 LSUnREG5 Field Descriptions LSUn Control Register 6 LSUnREG6 LSUnREG6 Registers and the Associated LSUsLSUn Control Register 6 LSUnREG6 Field Descriptions Completioncode BSYLSUn Congestion Control Flow Mask Register LSUnFLOWMASKS LSUnFLOWMASKS Registers and the Associated LSUsLSU n supports Flow 8 from table entry QUEUEnTXDMAHDP Registers RegisterQUEUEnTXDMACP Registers QUEUEnRXDMAHDP Registers QUEUEnRXDMACP Registers RxcpTransmit Queue Teardown Register Txqueueteardown Txcppiflowmasks Registers and the Associated TX Queues TX Queue n Flowmask Field Descriptions Queue n supports Flow 12 from table entry Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field DescriptionsTXQUEUECNTL0 Address Offset 07E0h TXQUEUECNTL1 Address Offset 07E4hTXQUEUECNTL2 Address Offset 07E8h TXQUEUECNTL3 Address Offset 07EChField Pair TXQUEUECNTL211-8 Mailbox to Queue Mapping Registers RXUMAPLn and RXUMAPHn 0890h Mapper Lettermask For a single-segment messageFor a multi-segment message LetterQueueid SegmentmappingFlow Control Table Entry Register n FLOWCNTLn Flowcntl n RegistersDevice Identity CAR Devid Device Identity CAR Devid Field DescriptionsDeviceidentity Devicevendoridentity DeviceidentityDevice Information CAR Devinfo Device Information CAR Devinfo Field DescriptionsDevicerev 31-0Assembly Identity CAR Asblyid Assembly Identity CAR Asblyid Field DescriptionsAssyidentity Assyvendoridentity AssyidentityAssembly Information CAR Asblyinfo Assembly Information CAR Asblyinfo Field DescriptionsExtendedfeaturesptr AssyrevProcessing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field DescriptionsSource and target of an operation. All PEs shall at minimum Source Operations CAR Srcop Source Operations CAR Srcop Field DescriptionsDestination Operations CAR Destop Destination Operations CAR Destop Field DescriptionsRead Write Streamwrite Writewith Datamess Doorbell Resp Andswap AtomicAddressing Processing Element Logical Layer Control CSR PellctlExtendedaddressingcontrol Lcsba Local Configuration Space Base Address 0 CSR LclcfghbarBit Field Value Local Configuration Space Base Address 1 CSR Lclcfgbar Base Device ID CSR Baseid Base Device ID CSR Baseid Field DescriptionsBasedeviceid LargebasedeviceidHost Base Device ID Lock CSR Hostbaseidlock HostbasedeviceidComponent Tag CSR Comptag Field Descriptions Component Tag CSR ComptagComponenttag Efptr Efid EfptrTimeoutvalue Port Link Timeout Control CSR Spltctl Field DescriptionsPort Link Time-Out Control CSR Spltctl Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Port General Control CSR Spgenctl Field DescriptionsPort Link Maintenance Request CSR n SPnLMREQ CommandSPnLMREQ Registers and the Associated Ports SP2LMREQPort Link Maintenance Response CSR n SPnLMRESP SPnLMRESP Registers and the Associated PortsPort Local AckID Status CSR n SPnACKIDSTAT SPnACKIDSTAT Registers and the Associated PortsPort Error and Status CSR n SPnERRSTAT Field Descriptions Port Error and Status CSR n SPnERRSTATSPnERRSTAT Registers and the Associated Ports Outputerrorenc OutputerrorstpInputerrorenc InputerrorstpPortok PortuninitializedSPnCTL Registers and the Associated Ports Port Control CSR n SPnCTLPort Control CSR n SPnCTL Field Descriptions Portdisable OutputportenableInputportenable ErrorcheckdisableRather than a parallel port Error Reporting Block Header Register Errrptbh Logical/Transport Layer Error Detect CSR Errdet RX I/O DMA access error Logical/Transport Layer Error Enable CSR Erren Pktresptimeoutenable UnsolicitedrespenableUnsupportedtransenable RxcppisecurityenableLogical/Transport Layer High Address Capture CSR Haddrcapt ADDRESS6332ADDRESS313 Logical/Transport Layer Address Capture CSR AddrcaptXamsbs Logical/Transport Layer Device ID Capture CSR Idcapt Msbdestid DestidMsbsourceid Sourceid MsbdestidLogical/Transport Layer Control Capture CSR Ctrlcapt Ftype Ttype MsginfoImpspecific FtypePort-Write Target Device ID CSR Pwtgtid Port-Write Target Device ID CSR Pwtgtid Field DescriptionsDeviceidmsb DeviceidPort Error Detect CSR n SPnERRDET Field Descriptions Port Error Detect CSR n SPnERRDETSPnERRDET Registers and the Associated Ports Protocolerror DelineationerrorLinktimeout RcvdpktnotaccptPort Error Rate Enable CSR n SPnRATEEN Field Descriptions Port Error Rate Enable CSR n SPnRATEENSPnRATEEN Registers and the Associated Ports Protocolerroren DelineationerrorenLinktimeouten PktunexpectedackidenPort n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 SPnERRATTRCAPTDBG0 Registers and the Associated PortsPort n Error Capture CSR 1 SPnERRCAPTDBG1 Description Case of a control-symbol errorCase of a packet error SPnERRCAPTDBG1 Registers and the Associated PortsPort n Error Capture CSR 2 SPnERRCAPTDBG2 SPnERRCAPTDBG2 Registers and the Associated PortsPort n Error Capture CSR 3 SPnERRCAPTDBG3 SPnERRCAPTDBG3 Registers and the Associated PortsPort n Error Capture CSR 4 SPnERRCAPTDBG4 SPnERRCAPTDBG4 Registers and the Associated PortsPort Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate CSR n SPnERRRATESPnERRRATE Registers and the Associated Ports Port Error Rate Threshold CSR n SPnERRTHRESH SPnERRTHRESH Registers and the Associated PortsDiscoverytimer PwtimerPort IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field DescriptionsRsten RstcsPwen PwirqPort IP Prescaler Register Ipprescal Field Descriptions Port IP Prescaler Register IpprescalPrescale Port-Write-In Capture CSRs SPIPPWINCAPT0-3 Port-Write-In Capture CSR Field DescriptionsPort Reset Option CSR n SPnRSTOPT Port Reset Option CSR n SPnRSTOPT Field DescriptionsSPnRSTOPT Registers and the Associated Ports PortidPort Control Independent Register n SPnCTLINDEP SPnCTLINDEP Registers and the Associated PortsSenddbgpkt IlltransenIlltranserr MaxretryenSPnSILENCETIMER Registers and the Associated Ports Port Silence Timer n Register SPnSILENCETIMERSilencetimer Multevntcs SPnMULTEVNTCS Registers and the Associated PortsBit Field Value Description 31-0 Port Control Symbol Transmit n Register SPnCSTX SPnCSTX Registers and the Associated PortsSTYPE0 PAR0 PAR1 STYPE1 CMD Csemb STYPE0Index Comptag Ctrlcapt Devinfo Pellctl Haddrcapt Lsuicsr 237 Pefeat 232 Srio Registers Rxcppicntl Rxcppiiccr Rxcppiicrr RXCPPIICRR2 Rxcppiicsr Broken link Degraded link Maximum retry error at port n Txqueueteardown Xoff Xon Important Notice